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How to correctly set the exchange between FPGA-cycles via FIFO (VST-5644R)?

Hello!
 
I created the Streaming Project (based on VST Streaming Project) in LabVIEW2014. Then I began to change it for myself. I need to make an RF transmitter. For simplicity, a simple project was created in which in the FPGA-VI a cycle of forming the IQ-quadratures was added (I=1, Q=0, but in the future a complex signal would be formed) and transferring by TargetScoped-FIFO to the Input/Output Loop (see app. "SimpleExample").

The created loop operates at a frequency of 5 MHz. In HOST, the frequency of the I/Q Rate (S/s) is set to 5 MHz. When the program is launched, the error Error-367000 is issued: The register read command timed out (see app. "Error").

How to correctly set the exchange between internal cycles of the FPGA through FIFO?

In the application I attach my project in the screenshots. The project in HOST uses "PRD VST Streaming (Host) PRD v2.vi", FPGA uses "PRD VST Streaming (FPGA) PRD v3.vi".

I am hope for your help. Sorry for my English.
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Hi AlexandrB, 

To ensure there wasn't a bad install or that the example wasn't corrupted, are you able to successfully compile and run the original, unmodified streaming example? 


Also, to clarify, are you only seeing error -367000 when you have the additional SCTL "SimpleExample" included in your FPGA VI? Without that loop does everything else work or are you still seeing that error? 
Additionally, do you see the same error message with something like a 40MHz clock wired to your SCTL in "SimpleExample"?

Shalini M.
Partner Development Engineer
Alliance Partner Network
National Instruments
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AlexandrB:

 

I'm not sure about the register timeout but there is one critical issue I see in this setup.  The VST Tx and Rx run in loops timed with data clock (the 120MHz ADC/DAC clocks).  I understand that you have the sample rate set on the host to 5MS/sec.  There is code inside the NI provided VIs that will do a sample rate change from 5MS/sec to 120MS/sec based on what you have set in your host.  So on paper all is correct.  The issue is that I assume you are deriving your 5MHz clock from either the 40MHz or 100MHz clock.  Those two clocks (Sample clock and whichever clock you used to derived the 5MHz) are not locked together.  That means the 5MHz clock is not exactly 1/24th of the 120MHz clock.  This will lead to FIFO overruns OR data underflows.  If you want to generate data at exactly the correct referenced 5MHz you will have to do it in a data clock timed loop.  Hopefully this explanation makes sense.

 

Andy

Systems Engineering - National Instruments
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shalumdawg:

Thank for the answer.

 

1) The newly compiled original example works well.

2) If I remove my SCTL from the project, then the whole point is lost, because the FIFO buffer in the Input/Outpute Loop cycle will have no data from anywhere.

3) I'll try to compile the project with the clock frequency of my cycle 40 MHz and later I'll tell you what will happen.
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AndyBrown:

 

Thanks for answer.

 

You're right. I form my 5MHz by dividing from 40MHz. The frequency 5MHz of reading data is from 120 MHz.

The main purpose is to synchronize two cycles - write data in my SCTL and read the data in the Input/Outpot Loop cycle.

You mean that I have to add my code to the main Input/Outpot Loop, running at 120 MHz?

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AlexandrB:

 

Sorry for the delay in response.  I read in another post that you had it working, great!  My concern was about the clocks not being exact.  So yes to be 100% correct you will need to write your code in the 120MHz loop.  I don't think you can derive a clock off of this120MHz data clock.  I don't know a lot about your application but one option is to run your 5MHz loop a little faster (i.e. 6MHz or 8MHz).  That would prevent overflows but then you would also have to add logic to handle underflows (clocks in which no data was present).

 

Andy

Systems Engineering - National Instruments
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