abc to dq transform

[longwu2000]

Hey evryone

I'm using GPIC doing a induction motor control. To do the vector control, have to use the abc to dq and dq to abc transformation.

However, when I put the high through put sin-cos function in the fpga vi, it takes way too many LUTS resources

I wonder is there a better way to calculate the sin-cos in fpga vi, which takes less fpga resources?

Thank you

Regards

Jia 

[dfjuggler]

Hi Jia, I did a quick test and found that this VI:

Generates these compilation results:

From my point of view, that seems like a reasonable amount of resources (target is 9606). In fact, the Sine & Cosine VI usage will be a bit lower than that, since these results include some logic for the front panel control and indicators.

Is that not the resource usage that you are getting? Might it be some other part of the abc to dq transformation what's having a high resource usage?

If you share your code, people might be able to provide more guidance.

[longwu2000]

Thank you for the reply, looks like we use the same vi. I dont know what casue the high LUTS usage

the figure above is the way i build the abc to dq and qd to abc trasnformatoin

i also attach the code

thank you very much

[BMac]

Keep in mind that the Xilinx compilation report tends not to give an accurate estimation of resource use unless the FPGA is close to full. It is perfectly happy to lazily fill up the FPGA if there is lots of space available. The reason is that it determines there is plenty of space available, and therefore does not "try hard" to minimize the resource utilization of your IP. Therefore, compile reports can be very misleading in the case that there is a lot of unused FPGA space. In this case, if the compiler meets timing constraints, it considers the job done (regardless of resource utilization).

To help get a more accurate estimate, you can change the compilation settings to force the compiler to work harder. To do this, right-click on your FPGA VI and create a build specification (if it doesn't already exist.) Then open the build specification (bottom of the FPGA project tree), and go to the Xilinx Options tab. Uncheck the box for Use recommended settings and change the Design Strategy to Timing Performance. This asks the compiler to work hard on all aspects of the compilation.

Next compile the FPGA application and observe the Final device utilization (map) report. I modified your IP core to use common fixed point data types for multiply, add and sine calculations where possible and then moved the math operations into non-reentrant (shared) subVIs. By resource sharing, this will make it slower due to resource sharing (multiplexing via arbitration), but reduce the resource utilization since only a single instance of a math operation for each data type is required. Typically FPGA IP is extremely fast, so sharing resources to reduce resource utilization is a good trade off. The FPGA block diagram and utilization report is shown below.

Non-reentrant execution (multiplexed shared resource) setting for subVI (File>VI Properties):

Compile report for DQ to ABC (Park) transformation (708 slices, 2 DSPs):

The code is attached.

[longwu2000]

thank you very much

[Brian_K.]

You can download resource efficient IP Builder versions of all of the most common transforms for power electronics here. Big thanks to NI systems engineer, Brian_K, for these!

This free, open source library includes efficient floating point (and fixed point versions) of the following transforms:

• ABC to alpha, beta (Clarke Transform)
• ABC to DQ
• DQ to alpha, beta (Inverse Park Transform)
• DQ to ABC
• alpha, beta to ABC (Inverse Clarke Transform)
• DQ to alpha, beta (Inverse Park Transform)
• alpha, beta to DQ (Park Transform)
• sine and cosine

Notes:

• In all of the functions, the units for theta are pi*radians rather than radians. In other words, set theta = 1 to represent an angle of 180 degrees or pi radians. Set theta = -0.5 to represent an angle of -90 degrees or pi/2 radians.
• To regenerate the IP, you need to have the Xilinx Compilation Tools installed and be running Windows 7 (ISE for sbRIO-9606, Vivado for sbRIO-9607). The Windows 7 requirement is a Xilinx toolchain limitation- sorry.
• The cores are set up in the project for the sbRIO-9607 (Zynq-7020). They can be converted to sbRIO-9606 (Spartan-6 LX45). After moving them, you'll need to regenerate the IP.

To learn how to use IP Builder to create highly resource optimized IP cores for LabVIEW FPGA, see this whitepaper. Please reply to this thread with any questions.

Here are screenshots: