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Need some help with the development of Level-Shifted (in-phase disposition) PWM for Five-Level Flying Capacitor Multilevel Grid-Connected Inverter.

I am confused on how to create four level-shifted triangular carriers with in-phase disposition. I am currently using the NI 7842R FPGA card.

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We are currently running a 6 phase DC-DC converter with clock frequency of 240MhZ and switching frequency of 200kHz on an sbRIO 9637.


Describe what you mean by level shifted and we may be able to help you out with our phase interleaving vi's.



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One more comment, this thread here  https://forums.ni.com/t5/Power-Electronics-Development/Phase-Shifted-Carrier-Signals-For-FCM-applica... is where we picked up the ideas to use the variable depth RAM based FIFO's to use the interleaving.  By converting back to fixed point and some other changes we have driven up the clock rate to 240MHz and are working towards 300MHz so we can get good duty cycle resolution with a switching frequency of 200kHz.

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Hello Dave,

Thanks so much for your quick response. The Level-Shifted means in-phase disposition PWM, I have attached a picture below. I am also open to the phase-shift PWM idea. I will check the thread shared and get back to you on my findings. Thanks so much.

Image result for Five-Level Shifted PWM

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Ok, now I understand that level shifting is not another way of saying interleaving.  We are just doing interleaved PWM square waves for a DC-DC converter so our code is not much help.


Is the picture you attached for controlling a 3 level inverter.  If so I imagine for each phase you need one sine generator and 4 triangle generators with each triangle generator having its own min and max, in the case of the picture (-1.0 to -0.5)(-0.5 to 0.0),(0.0 to 0.5),(0.5 to 1.0).  These all get compared


For a 3 phase inverter the outputs of the 4 triangle generators can each be offset by variable depth RAM based FIFO's per BMAC's note in the forum post I forwarded.  Offset twice with the variable depth FIFO's, 120 degrees for the first offset phase and offset those again 120 degrees for the third phase.  All 12 triangle generators being compared with the single sine wave to give you 12 outputs to drive a 3 phase 3 level inverter.


Let me know that my understanding of your picture and the 3 level inverter is correct.  I've been introduced to 3 level inverts as a way to use common 1200 volt class IGBT's on a future drive system we will need to operate off of a 1500Volt DC buc, but except for the schematic diamgrams I hadn't given much thought to how you would control one until I saw your picture.


You mention a 5 level inverter, so will that have 8  triangle generator from top to bottom instead of the four in the picture?



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Message 5 of 9

Hi Dave,

The diagram is actual for a five-level inverter. For a five-level multilevel converter, you have four pairs of IGBT modules; each carrier (triangular wave) represents the switching of a pair of IGBT module. Therefore, a single phase will have four triangular waves compared to a sine wave.

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Message 6 of 9

Got it now, it took me a while to get my head around the 2 level, 3 level and 5 level.  I basically took the 2 level SPWM code and modified it to work as a simple interleaved PWM generator for variable duty cycle square wares instead of AC sine waves.


I was partially wrong in my reply, you can shift the four triangle generators, but its typically the 3 sine waves that you shift with the variable depth RAM FIFO's.  Then do 12 comparisons and drive the 12 digital outputs to control the 12 half bridges.  Or 24 digital outputs if your half bridge gate drives don't automatically do complimentary switching with built in dead time.


While we are getting a 240MHz clock rate with the triangle generator code and fixed point variable depth RAM FIFO's, the sinewave generators are likely to slow that down and also the deadtime or delay IP that was in the sample code I pointed you to.


Your original question had to do with the 7842R FPGA card, I did look that up, the manual was from 2009 and it may use an older FPGA chip than my brief experience on a sbRIO 9637 has exposed me to.   I suggest looking up the open source GPIC code and seeing if it will operate on the 7842 and then start modifying the triangle generators to get your 5 level SPWM code working.




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Message 7 of 9

If you still need help.

For 5L inverters you need 4 carriers if you do not want to modify the modulating signals to operate with only one carrier (it is usually done with DSP and uC).

I usually build an up/down counter on the FPGA target, placing it inside a SCTL running at a reasonable higher frequency (creating a dedicated clock domain) than the switching frequency.

The up/down counter is the first carrier. After that you have to translate vertically the first carrier in order to generate the additional 3 signals. It is just 'sum' and 'subtract'.

Of course you must work with integer data type. Nothing new, the single carrier PWM units of DSP and uC works more or less in this way.

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