Speaker: Kevin Wenner (AE Specialist, National Instruments)
LabVIEW offers several tools to help you simulate your FPGA code. At this session, discover how to take full advantage of these tools to reduce your need for frequent time-intensive compilations. Learn how to include IO stimulus, target/host interaction, and other features to spend more time developing and/or testing code and less time waiting on compilers.
*KAW Edit: I just added the presentation PowerPoint for those that are interested!
Any chance of a PDF or PPT of the presentation for those who couldn't attend?
Just updated the OP with the presentation PPT!
Hmm, the statement that CLIP IO nodes can't be simulated is not strictly correct as far as I know. I'm referring to Slide number 44.
It's possible to create a template VI for custom handling of inputs and outputs (adding noise, delays and so on). It's difficult, but it's do-able and I've used it in the past. It's great for testing.
Intaris, you are definitely correct that it's possible to use a Custom VI for simulation I/O stimulus of CLIP items (and other things). I didn't cover it in my presentation because it is quite a bit more complex to set up, compared to the DEN, and I didn't have enough time to adequately cover it. In addition, the Custom VI examples were removed from newer version of LV FPGA (for some reason), so I didn't really have anything to which I could point people. While the tool still exists, the feedback I got from R&D was that we were hoping to push people towards the DEN.
For those interested in finding out more about simulating I/O with a custom VI, here is a tutorial from the LV 2016 help:
https://zone.ni.com/reference/en-XX/help/371599M-01/lvfpgaconcepts/test_bench_tutorial/
*EDIT: Also, thanks for the feedback Intaris!
Oh, I guess I should mention that the point of slide 44 is to illustrate that the actual VHDL of the CLIP is not simulated, and thus you get random values back unless you hijack the I/O through the Custom VI or by swapping the I/O node with a control and using the DEN.
In contrast, slide 43 illustrates that when you add your VHDL to an IP integration node, the Xilinx compilation tools build a model of the VHDL that LabVIEW calls. Therefore VHDL in an IP integration node it is actually simulated, whereas this process does not happen for CLIP, so CLIP it is not truly simulated in LabVIEW.
Sorry for any confusion!
That's OK, I think the clarification is very useful. I might propose adding it as a footnote in the presentation. the only reason I spotted this is because I went through the pain of implementing such a solution for our FPGA code during a re-write last year. I agree the process is complicated but when the penny drops, the results are actually pretty cool.
I was actually not aware of the different handling of the two modes you describe. Thank you, it's useful information.