When the next sampling clock comes, the DAQmx writing is not completed; it indicates that the user program can not keep up with the hardware clock.

[好人脸]

hello, everyone. I have connected the AMESim model at the rate of 1000hz to the AO0 of PXIe-6366, the AO rate of PXIe-6366 is the default value, then I tried to deploy the project, but it seems that the software rate is too low. the details are as follows:

there are some message of the log: 

Details:
Error -209801 occurred at Project Window.lvlib:Project Window.vi >> Project Window.lvlib:Command Loop.vi >> NI_VS Workspace ExecutionAPI.lvlib:NI VeriStand - Connect to System.vi

Possible reason(s):

When the next sampling clock comes, the DAQmx writing is not completed; it indicates that the user program can not keep up with the hardware clock.

Please slow down the hardware clock or modify the user program to keep up with the hardware clock.

but how to change the hardware clock, like pxie-6366?

[carmen9]

Hi,

Can you please attach your VI?

You can have a look at this post:

https://forums.ni.com/t5/LabVIEW/Timed-loop-Error-209801/td-p/2842014

[好人脸]

ok，thank you carmen9 , I will look it carefully

but I only use Veristand 2014 instead of labVIEW, so there is no VI.

thanks again