Throughput PXI - FlexRIO

[riccolisi]

Hi,

I have a PXIe-1085 12 GB/s providing a maximum nominal single-direction bandwidth per slot of 4 GB/s.

Then I have a FlexRIO 7976R 3.2 GB/s on slot 4. 

I use FIFOs to communicate between Host controller and FPGA.

In the worst case of my application I have a throughput from Host to FPGA of 262 MB/s and a throughput from FPGA to Host of 2.88 GB/s.

Hence, the total throughput is 3.142 GB/s that is less than 3.2 GB/s. 

In this condition I have an undesired behaviour with loss of data.

If I reduce the input througput from Host, the output throughput also decreases and everything works well.

I have also also controls and indicators in my FPGA loop that are read/written each iteration (180 MHz).

But from Host I don't read/write from/to these controls/indicators during FIFOs transfer.

My question is:

In the throughput calculation, should I consider even the writings/readings of FPGA controls/indicators that are not used from Host?

Thank you!

[Terry_ALE]

FPGA controls/indicators tax the CPU (as they are being continuously updated).  The rate that the FPGA updates them should not matter since it is the RIO drivers that manage that.  Also these items are updated in a lossy way and will only impact things if you have too many.  Too many is said to be in the 100s but I do not know a specific threshold.