[Synth 8-5809] Error generated from encrypted envelope.

[Ct93]

Hello everyone!

I am currently using a NI PXIe-1071 with PXIe-8840 CPU and PXIe-7868R FPGA module as HIL, running OPAL-RT eHS-64 solver.

The project created in Labview 2019 compiled correctly. Then, we decided to upgrade to Labview2021 and the attached error "XilinxLog.txt" came.

It is not a problem related to the programs/add-on installed on the PC because we are able to successfully compile other projects (related to CompactRIO used as HIL with the same LV2021 project and sbRIO-9651 devices).

It seems an error of the Xilinx compiler with the specified hardware.

The first suggestion found (https://forums.ni.com/t5/Hardware-Developers-Community-NI/sbRIO-9609-not-able-to-compile-CAN-amp-FPG...) didn't help solving the problem.

While we were not able to apply the second suggestion (https://support.xilinx.com/s/article/54317?language=en_US) through the Component-Level IP wizard.

Do you have any suggestion?
Thank you in advance!

[Terry_ALE]

Comment out different parts to see which one is causing the issue.

Does any Xilinx IP need to get regenerated?

Does the OPAL stuff work in newer versions of LabVIEW?

[heel]

In case other sees the same error - here is what solved it for me:

It turned out that error [Synth 8-5809] was due my mistake.

Had instantiated a write to Target-to-host fifo twice. The fifo was in arbitrate never mode. It would maybe (/ought to) have compiled with arbitration active - which would have concealed my mistake - as this was not what I wanted I did not spend time in checking.

Selected the correct pair of FIFO's and all is good.