Synchronizing clock edge with data position

[Ryan_M]

That's great news!

The 6562 is a dedicated differential LVDS device so it is always expecting a differential signal.  The LVDS specification says that the differential swing must be larger than +/-50mV and should not exceed an absolute voltage range of 0V to 2.4V.

The 6562 has an associated connector block called the SMA-2164.  This takes the differential cable and breaks each signal out to a individual SMA coaxial connectors.  More information on this solutions can be found at:

http://sine.ni.com/nips/cds/view/p/lang/en/nid/201705

The best results will be achieved by driving differential signals to each of the pair of SMA.  However, if you only have single ended signals available that are within the specifications of the absolute input range then you could simply drive that single ended signal to the postive terminal and a signal at roughly half the swing to the complimentary.  You do not gain the benefits of a differential signal in terms of canceled crosstalk and EMI but you do drive the differential stage such that the logic will toggle.

Does that make sense?

[Ryan_M]

One other thing to note with the SMA-2164.  Each channel pair has some component pads that allow for some alternate signal routing/termination.  The documentation goes into further detail of these connections but if your single ended signal is outside of the specified range, you could uses these pads to add some signal attenuatation such that the signal presented to the 6562 is within the specifications. 

If you have any questions on that sort of implementation, read through the documentation and let me know if you have any questions!