Maybe you can reduce the jitter but may not up to the 100ns variation you require.
83 sample delay is due to the filter at the front end of the Delta-sigma DAC of 4463. For DSAs the sample clock is always onboard clock due to their oversampled nature and free running. You can configure the PXIe_CLK100 as a reference clock (not the 10MHz on a PXIe chassis).
Triggers sent on PXI_TRIG line are always 100ns wide (1 clock of 10MHz), in addition to this, each instrument has its own delay to process this trigger and react, hence it cannot be faster than 100ns on a PXI_TRIG line.
It is worth trying to make the DSA as the trigger source and let the 6570 react to that trigger instead of the other way around.
What does this 6570 and 4463 connect to, what is the DUT and setup, why do you need the 100ns synchronization?