I've decided to post to the forums while I wait for help from NI.
I've searched through the support, community, available documentation, and NI examples, but none seem to quite capture what I'm trying to do.
To describe the situation as simply as possible, within PXIe-1082 chassis (with a PXIe-8861RT controller), there is an FPGA card (PXIe-7858R) and a sound and vibration module (basically AI module, PXIe-4492, let's call it "secondary acquisition card"). From the FPGA, I'd like to trigger acquisition in the secondary module. I have not found a way to do this.
PXIe7858R lies in slot 6.
PXIe4492 lies in slot 2.
Here's what I've done and tried.
1) Created a resource on the FPGA for PXI_Trig0 line (I had also done this for PXI_Trig1 line just to try a different one)
2) I wrote a simple FPGA code where I can toggle this line:
- True cases uses PXI_Trig0 resource.
> Originally, I had the Acquire control as a latch with a 100us wait inside the while loop (backplane triggers must be at least 9ns, so I just went with some reasonable "big but small" number), but we ended up changing it to just switch when released to ensure we are really holding it high for long enough while we do this debugging.
3) RT code:
I setup my 8AI channels for acquisition of set number of samples that are configured to measure at a digital start:
- The analog acquisition has a default time out of 10 seconds during which we wait for the trigger.
- False case in case structure is just wired through, was making sure that the task is setup up properly etc.
Two things you might observe:
1 - I am choosing PXI1/Slot2/PXI_Trig1 as the source for the digital start edge. After talking with NI support, because the chassis we are using is only 8 slots (PXIe-1082), all the trigger busses should be "connected," therefore if I am generating a trigger via Slot6 with PXIe-7858R, a card in slot 2 should be able to read from its PXI_Trig1 resource and see the same values. We both thought it was odd that the source options all specify the slot since it should all be connected. We tried reading from "PXI1/Slot3/PXI_Trig1) as well just to try a different "slot line."
> Additionally, only slots 1-3 show up as available resources, not slots beyond (beyond are two cards, slot 6 my 7858R FPGA card and slot 5 a digital IO module PXI-6515).
Full PXIe slot contents here:
> Available sources to choose from:
With NI, we eliminated that there shouldn't be any need to route the triggers to one another (as I wondered if that's something we need to do as well).
Before someone else says it, yes, we do have a workaround to use: output a signal from 7858R DIO line and route it into the 4492 PFI 0 line and trigger that way, but that is not a long term solution for us.
One question I have is, is it not possible to use backplane triggering between an R series card and non R series card?
I appreciate any input or help.
I can upload the two VIs that are screenshotted here if needed, but I figured those might be useless unless someone has the hardware or similar set up to test with - can do if requested.
Solved! Go to Solution.
Interesting, I would have assumed that the PXI Bridge routing be the root cause but it makes sense that there is only one bus segment on an 8-slot chassis and hence no PXI Bridge routing is required.
I would try typing in "/PXI1Slot6/PXI_Trig1" as the trigger source, though you could not see it in the list, if it is feasible PXI Platform services should definitely route it.
I appreciate the suggestion. I just tried it and I got an error after DAQmx Start Task - No device by the given name was found. It was worth a shot.
I saw references to PXI Platform services in some knowledgebase articles, however, they all referred to again routing the backplane lines which we shouldn't have to do for this chassis. Even though we shouldn't have to, I wanted to see what the options were, but when I select chassis from NI MAX project tree, I don't see the triggers routing options like that knowledgebase article I saw (can't find the article at the moment). I have PXI Platform services on both the host and the controller, so not sure if something is in fact missing beyond that.
Wow, this worked! Just when I thought this is hopeless.
Kuddos to @iron_curtain and an old thread that was the only one closest to my issue in this forum (https://forums.ni.com/t5/PXI/How-to-connect-DAQ-and-FPGA-through-PXI-chassis-backplane/m-p/3683301) . Though not exactly the same, his FPGA snippet showed me the Set Output Enable option, after I setup the flow as in my screenshot above, this worked!
Hope this saves someone else 2 days 🙃