PXIe-8108 Lane Allocation

[RoyZ]

Questions on Lane Allocation when PXIe-8108 Configured as 4-Link:

 
1)  When PXIe-8108 is configured as 4-Link, I know that each Link has only one Lane available. I suppose the Lane allocation is in the way that the first Lane, Lane0 (i.e.,  xPETp0, xPETn0, xPERp0 and xPERn0 pairs, where x=1,2,3 and 4 respectively) of each Link is the available one. Is this understanding correct? 
 
2)  In terms of Lane0 of Link4 on PXIe-8108, I suppose that it is the specific "channel" that connects to a PCIe-to-PCI bridge. Is this understanding correct?

[ericg]

Hi Royz,

1) You're right, on the PXIe-8108, each link is comprised of a single lane.  In other words, each link has a maximum width of x1.  This is true in 4-link AND 2-link modes.  In 2-link mode, there are two x1 links (links 1 and 3) that remain active.

2) On any PXIe controller, the routing of a given link is a function of the backplane more than the controller.  Each backplane (PXIe-1062Q, PXIe-1065, etc.) can route links differently.  On the chassis you're using, link 4 probably routes to a PCIe-PCI bridge that implements the PXI portion of the chassis' hybrid slots.

Hope this helps.  If you need further clarification, please feel free to ask.

Thanks,

Eric G.

National Instruments R&D