PXIe 4140 current offset

[bbentelin]

I've been using the PXIe 4140 to measure Current/Voltage curves for transistors --- it sets a voltage & I read out current (not necessarily on the same channel).  But I'm noticing a peculiarity in the data depending on the current limit. 

Firstly, I get different results if I let the device autorange versus manually setting the current limit. 

Particulary, there is an current offset which occurs for differnent current limits.

In the attached file the current is allowed to autorange for the red data, and set at 100mA for the blue data.  [the  axes are drain source current - IDS -- & gate Source Voltage - VGS]

Any idea what's causing the .02mA offset in the red data?

[SSPTest]

<Deleted>

[Wild_man]

It's a bit difficult to tell based solely on the graph but it looks as though the current autorange may be setting the current limit at 100uA for both channels. This would cause the SMU to go into compliance which would usually turn the LED on the front of the SMU yellow during the test.

Could you plot Voltage versus Current for each channel independently? This would allow us to see if we are running into a current compliance issue.

[bbentelin]

The channels aren't on the same SMU but I'll just label them CH1 & 2 for now.

Again, typically we scan the voltage on CH1 & read the current measured on CH2 though CH2 is kept at a constant voltage.

[Wild_man]

Are those graphs with the device auto-ranging or with the current limit set manually?

[bbentelin]

Let's start over  ----

I'm getting all sorts of irreproduceable results, here are my recent tests (all plots show current versus voltage):

There are 28 transistors to test - I have a vi that goes through each in sequence as well as a vi that can test a single transistor.  (I need 2 SMUs to test a single transistor & 8 to test all 28)

Yesterday I was getting the same results using both vis.

But I've tested the transistors using both an NI PXIe-1075 18 slot chasis & a smaller chasis with just 2 SMUs, and the results differ ("big v small")

To see if it was the number of SMUs connected, I did the single transitor test on the big chasis with 2 SMUs, then added more SMUs up to the orignal 8 I had plugged in.

At first the IV curves go way down when I took out the SMUS ("2 v 8 SMUs compares the orignial data with 8 SMUs to the data with 2 SMUs)

But then there was no correlation of the data with the number of SMUs connected (# of SMUs).  And the data with 8 SMUs did not reproduce.

The current offset is noticeable in that plot as well, though the current limit is set to 100mA for all those measurements.  So it isn't just to do with the autoranging - any guess what's causing it?

[bbentelin]

I then did the multi transistor test again to see if all the SMUs needed to be initialized to have an effect.

And I subsequently did the single transistor test again.

None of that data agrees - "single v multi" shows these tests in sequence

Any clue how these SMUs are affecting each other?  I had assumed that the chases are capable of handling as many SMUs as there are slots - but is that the case?  Do they draw any current just being plugged in?

[Wild_man]

It's hard for me to say why they might be affecting one another, as I would not expect them to. It would be good to check to verify the chassis can support that many SMUs. I've linked an article below that details the procedure to do so.

Performing a Power Budget on a PXI System

http://digital.ni.com/public.nsf/allkb/054105B2AAEACD3486256FDC00579A72

What behavior would you expect from the DUT? Can you provide an example graph or point to a datasheet of a comparable PMOS transistor that shows the expected behavior?

[bbentelin]

I apologize this has run on for so long --- I had been working at another institution for the last few weeks.

I belive the issue is this:

Some transistors break as we are doing radiation tolerance testing.  That opens up connections for leakage currents, and thus, although the SMUs are reportedly outputting the correct voltages, the transistor under test is not receiving the full voltage.  I was seeing higher gain in the transistor IV curves using 2 SMUs instead of 8  SMUs because the broken transistor aren't connected into the system with just 2 SMUs, & so no leakage currents.

I found that if I open the NI Power soft panel for an SMU atttached to a broken transistor (with all channels' outputs enabled),  there is a current draw to the channel connected to the broken transistor.

Is there a way to deal with this through software?  What occurs in the SMU when I enable / disable a channel's output?

[Hey.itsDale · Accepted solution]

Thanks for following up with an explanation.

It looks like this resource addresses your question:

http://digital.ni.com/public.nsf/allkb/EE869FC813944EAC862578F0005519F5