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PXIe-1082 Backplane Clarifications

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We are potentially looking to implement the PXIe-1082 backplane into a custom chassis.  The installation guide (373001a.pdf) is vague in certain areas and we would like clarification on the following items:

 

Q1:  The installation guide discusses the J35 pinout but does not identify the mating connector manufacaturer/part number.  Can the mating connector be identified?

 

Q2:  Can it be assumed that signal LED1 only exists between J37-14 and J35-3?

 

Q3:  Can it be assumed that signal LED2 only exists between J37-15 and J35-4?

 

Q4:  Can the signal denoted PS_OK in the J37 pinout be assumed to be synonymous with PWR_OK as defined by the PCIe specification?

 

Q5:  Can it be assumed that the OVERTEMP# signal is a TTL compatible output signal that is low when an over temperature condition exists?

 

Q6:  Can it be assumed that signal 12V_FAN only exists between J37-20 and test header W1 pin 7?

 

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Accepted by topic author TheEngler

Hello TheEngler,

 

This is Saki from Applications Engineering at National Instruments. I am looking into your questions but I would like to get a bit more information about your application in order to determine if the assumptions are valid for your specific application. If you don't feel comfortable sharing that information in public, please feel free to send me a direct message. 

 

Cheers,

Saki K.
Applications Engineer
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