05-04-2011 03:37 AM
Hi All
I'm using a PXI-5422 Signal Generator board in finite generation mode to generate a signal on external trigger (PFI0) approximately every 5ms. There is a nominal 1.7µs delay from the trigger input to the start of generation. This in itself is no problem (I can compensate for the delay), but there is up to 50ns of jitter on this delay, which is a problem. Does anyone know if there is something I can do to minimise this jitter? (Incidently, PFI1 exibits the same behaviour, but this is no surprise)
Many thanks
Solved! Go to Solution.
05-06-2011 12:54 PM
Hello GVR123,
I had a quick look at the manual for the PXI-5422 and I found the note for the "Delay from Start Trigger to CH 0 Analog Output" which is stated as "65 sample clock periods + 110 ns". With this information I calculated that
1.7-0.110=1.59
and
1.59/65=0.025 (roughly)
which points to a 40MHz clock. So I assume this is what you are using.
The 25ns (40MHz) deviation either side (50ns total) you are seeing is therefore expected, as there is no way to make sure the trigger falls exactly on a rising edge of the sample clock.
I hope this helps.
Kind Regards,
Michael S.
Applications Engineer
NI UK & Ireland
05-09-2011 02:55 AM
Hi Michael
Thanks for your reply. I must admit that when I read that, I neglected to read the fact that it is 'sample clock' periods. Your deduction of a 40MHz clock is indeed correct. I have increased the sample rate to 200MHz and as expected the jitter is substantially reduced.
Thanks again.