PXI 6583 DIO state when configured for driver

[DanSellman]

I am using a PXI 6583 IO module connected to a 7953R FPGA for running test program communication using LVDS. Upon power up of the PXI there is no common mode voltage on the DIO output lines on the DDCB connector DIO lines. After initializing our FPGA target we now see approx 2.2V common mode on both + and - sides of a DIO diff pair when open circuited at the receiver end. We continue to see this forever until we power down the PXI chassis and reboot. Our problem is that when these lines are connected to the receiver, the receiver has no voltage on it's VCC rail. This presents us with a problem as some of these lines have ESD diodes to this VCC rail, which when un-powered are becoming forward biased and charging of the VCC rail is happening when its VCC is in a high z state. We can't seem to reset the IO module to return to an un-driven state when the program is complete so that the next time we connect something, these lines are back to an un-driven state. If we could, we could then make sure to power up the VCC on the receiver end before we begin using the IO module. Is there a way to return the outputs of the 6583 to an un-driven High Z state via SW? 

Dan

[Stop_Luke_and_Listen]

Hi Dan,

The behavior you are seeing is the result of a built in Fail Safe in the TI SN65LVDM180 LVDS receiver.  It returns all high values when the line is disconnected or not being driven.  You can learn more about it in this KB: https://knowledge.ni.com/KnowledgeArticleDetails?id=kA00Z0000019MkISAU.  There isn't a way to bypass this functionality in software.

[DanSellman]

Thanks for the response, we actually found a way to disable the IO module power and then load a dummy bitfile without support for our 6583 module, this did the trick to turn off the IO module power. The other thing I was questioning was that I understand the function of the TI LVDM180 when disconnected; I assume you are referring the "failsafe" feature. The one sticking point was that in my understanding of the failsafe it should pull the lines to 3.3VCC through a 300k pull up, but we were seeing 2.2V common mode on pins. I assumed that this was possibly the current driver set to drive an LVDS pair but open circuit so just sitting at the current drivers VOC value.