I have a question about the documentation in Configuring GPS Synchronization with the NI PXI-668x Timing and Synchronization Module. Under "Single-Board Disciplining with the PXI-6683H", there is a description of how one configures the PXI-6683H by connecting some clock terminals internally and then connect a SMB-BNC cable from the PXI-6683H clkout port to the chassis PXI 10 MHz clock input port.
The two clock connections one makes internally are:
What functions does the BoardClk perform and where does it exist in this diagram from the PXI-6683 user manual (shown below)? Is this the clock source that produces timestamps for the NiSync Get Time VI? Is it at all used to in a feedback loop that disciplines the TCXO?
So this leads me to a question about expected behavior. In the use case of 'Single-Board Disciplining with the PXI-6683H', one would generally assume that there is a good connection from ClkOut to the Chassis PXI 10 MHz input. But what if there was no connection here (e.g., someone forgot to connect it, or it came loose)? Then obviously the PXI backplane clock is free-running. But does this also mean that the timestamps from the PXI-6683H would be made off a free-running timebase rather than one disciplined to GPS? I would hope not, but just want to make sure.
Basically I'm concerned about the possibility that if I follow this guide in my system design, but a technician fails to connect the external cable, how worried should I be that the event timestamps that come out of the system are less accurate in some way? I see a lot of references to "board time" in the NiSync documentation, so that makes me think that this time is coming from the BoardClk.
PS. -- Just for reference, this is a follow-on to a previous post, Access to PXI-6682H TCXO 10 MHz oscillator signal.