IO Module Clock 1. NI 6587

[incisive]

how to acquire external lvds clock on labview. I have used IO module clock 1 and connected to single cycle timed loop. In 40MHz timed loop i enabled the xpoint switch and set IOmodule clock 1 source to strobe bypass. I have also set the properties in Adaptor module settings. i am acquiring clock on stobe signals through SMA 2164 board.

Yet i am getting error that the host and fpga are not able to communicate. clock not detected.. the error which appears when clock is not being detected.

WHere am i wrong? need help

[HizNI]

Could you attach a screenshot of your code and Single Cycle Timed Loop? I am having trouble visualizing what is going on.

[incisive]

this is how i am using external lvds 50 mhz clock for acquisition. but i receive an error..clock not detected. host and fpga communication error. how to use external lvds clock in basic connector?

[incisive]

I want to know how to enable external lvds clock when using basic connector in fpga.vi . I have used io module clock 1. set it to 50MHz in properties and enable xpoint switch write as shown in attachment. please see and tell me why is my clock not detected.

[diabeticdaniel]

Have you tried configuring your clock source settings before trying to use the IO Module 1 clock in a SCTL? What I mean by this is that rather than having two parallel loops, you should have your configuration loop happen before you try to use the clock. I would try looking at the NI 6587 Finite Acquisition - External Clock Start Trigger.lvproj example. This example uses the Serdes CLIP rather than the basic one, but it still should give you an idea of how we expect this configuration to occur on the FPGA.

[incisive]

yeah the serdes clip example runs ok. I ammended the same VI for basic clip but the clock is not detected. It would be really nice if you help me out. 

[a_clucker]

Hi incisive,

Could you please attach a screenshot of the error as well as the Clip configuration you're using?

Also, are you making any modifications to the example diabeticdaniel recommended?

[incisive]

Ok..I am finally able to get the clock..but there is one problem..
the code runs properly if I run it at 50MHz clock using IOmoduleclock0 (the external single ended clock). whereas when I use IOmoduleclock1, it gives error. when I reduce the size of the code, that is remove the dma fifo and replace with indicator, it works fine. why is that so?

[Cooking_Up_Code]

Hi incisive,

Can you please provide some more details on the error you are experiencing? Are you getting this error during compilation? It may be that you have too much logic in your Single Cycle Timed Loop and it cannot all be executed within one clock cycle. Slowing down your clock speed is one solution to this issue. Implementing feedback nodes may also help. This will allow you to store data between clock cycle iterations. Check out section number 8 in this tutorial for more information on implementation.

http://www.ni.com/tutorial/14532/en/#toc8

[incisive]

I have implemented feedback nodes and now I am not getting error of Timing violation. 

The code compiles but I am again not able to detect the clock. What can be the problem?

The error I am receiving and the fpga VI is attached below. Please note that I am using basic connector configuration for adapter module.