How to create a D flip flop and its clock using LabVIEW FPGA

[Vsscisro123]

I am using a PXI 7846 Multifunction RIO. How to create an edge-triggered D flip flop (rising or falling edge) and the clock to the flip flop is a 200MHz clock that needs to be internally generated from the LabVIEW FPGA. It is my understanding that the high-speed clock can be generated as a derived clock. But how to use this clock to drive a D flip flop and how can a D flip flop be implemented?

[ZYOng · Accepted solution]

Replace the while loop in D-Type Flip-Flop with a Single Cycle Timed Loop timed by a derived 200MHz clock.