How to connect DAQ and FPGA through PXI chassis backplane

[iron_curtain]

Greetings,

I'm trying to use a NI DAQ (PXIe-6356) to control a FlexRIO FPGA (PXIe-7972R), or the other way around, through PXI chassis backplane. To be more specifically, I'd like to generate a digital pulse (for example a line clock) from one device and use it to trigger the other device (to start data acquisition) in the same PXI chassis. 

I could do that by connecting the corresponding DIO terminals with an external wire but that would affect the signal integrity and cause timing delay. There are some articles online talking about using PXI_Trig through PXI chassis backplane to sync different PXIe devices, but in DAQmx was not able to expose any PXI_Trig terminals (only port0/1/2 lines are available).

Did anyone have any experience with sync'ing DAQ and FGPA with PXI backplane? Any advice would be greatly appreciated.

Thanks very much!

-Bing 

[crossrulz]

For the trigger pulse to start an acquisition on the DAQ, there is a DAQmx Configure Trigger.  With that VI, you can specify a PXI trigger line as the start trigger.  On the FlexRIO side, you need to create a new FPGA IO to access the same trigger line.  You can then write to that line to start the DAQ.

Similar procedures to be used for sharing clocks or start triggers going the other way.

[iron_curtain]

Thanks very much for your reply. I created an example based on your suggestion and LabVIEW DAQmx Voltage (with events) example.

The screenshots are attached. 

When I disabled the FPGA call in the host vi and run the DAQmx task and the FPGA vi as two separate VIs, I was able to use FPGA to trigger DAQ acquisition through PXI_Trig0, if I started the host vi and then set PXI_Trig0 to True in the FPGA vi.

However, when I tried to run DAQ and FPGA in the same host vi (i.e., enabling FPGA call), most of the time switching PXI_Trig0 to True couldn't trigger DAQ (although it worked randomly sometimes). 

Did I miss anything?

Thanks,

Bing

[James_McN]

From memory I think the PXI lines idle high. That means to trigger the DAQ you actually need to set a false on the PXI trig line, not a true.

This is based on a distant memory so it could be wrong, but there was something like that.

Otherwise what chassis is this? Larger chassis (18 slot certainly) have the trigger bus split into segments and you need to configure them to pass the trigger through in MAX or move the cards closer together. They are marked by vertical lines between the slot numbers on the front of the chassis.

[James_McN]

Oops not quite right - they run tristate (which appears high to the FPGA) - you need to enable the line separately first. See http://digital.ni.com/public.nsf/allkb/A639B5A8EFFF1717862578A9006F643E

Also you should reserve the lines - see http://zone.ni.com/reference/en-XX/help/373197D-01/target2devicehelp/reserving_triggers/

[iron_curtain]

Hi James,

Thanks for  your suggestions. To answer your question first, I use a small PXI chassis, PXIe-1073 to be more exactly, so there is no segmentation issue

I followed the links you sent and rewrote the code. However this time I cannot trigger the DAQ no matter I set PXI_Trig0 to true or false, if I placed the FPGA call and the DAQmx code in the same host vi; I could still trigger DAQ if I ran the FPGA code and the DAQmx code as two separate VIs though. Any thoughts?

Thanks,

Bing

[TheresaM]

Hello,

I have happened to run into the same issue and it's been pretty difficult finding the solution. Your post is the closest I got to someone having a similar problem (R series card triggering a DAQ card through backplane chassis). Were you able to resolve this?

I appreciate any help.

If this is not the place to do this, I made a forum post as well: https://forums.ni.com/t5/PXI/R-and-non-R-series-PXIe-card-Triggering-via-Backplane-Generating/m-p/41...

Thank you,

Theresa

[TheresaM]

Thank you for your snippets! It gave me the right idea to modify my code and I got my FPGA to trigger the DAQ acquisition through the backplane, yay!