How do you configure multiple PXIe chassis to share Tclk synch with the 6672 timing module?

[Cillian]

Hi,

I have two PXIe chassis, each with a number of digitizers (configured through NI-SCOPE). Each chassis has a PXIe 6672 timing module. I have downloaded the sample VI from:

http://zone.ni.com/devzone/cda/epd/p/id/5254

which deals with PXI chassis. My question is this: in the VIs at the above link (and in fact all VIs I've seen for using the 6672 for sharing triggers), the VI needs access to the resource identifiers for both Master and Slave timing modules, how do I access the (remote) slave resource identifier from the master chassis? I feel like I'm missing something obvious, but can I do this using just an ethernet connection, or do I need another module to enable the master chassis to view the devices on the slave chassis in MAX? 

Thanks for any help you can provide,

Cillian

[The_Red_Barron]

Howdy Cillian!

How are you controlling the two PXIe chassis?  Do you have an embedded controller in each chassis or are you using a host PC connected via MXI?  If you are using a host PC with MXI are the PXIe chassis in a star configuration or are they daisy chained?

Regards,

[Cillian]

Hello Barron,

Thanks for the response.

Each chassis has an embedded controller. The only connection between the chassis is through the SMB cables connecting the 6672 modules.

Is it even possible to use the sample VIs with this sort of configuration?

Cillian

[The_Red_Barron]

Those example VIs are written to be used when a single host PC is controlling multiple chassis so there is just one computer running the program.  Since both of your chassis have their own controllers it will be necessary to run a program on each (one as master, the other as slave).  You can modify the code from that example to create and Master and Slave VIs.  For the Master you will call the VIs as specified in case 0 of the example; for the Slave you will call the VIs as specified in the default, 1 case of the example.

You will also want to send a signal from the Master to the Slave to let the Slave know that the clock is being generated.  You could use TCP/IP or a PFI line to do this.  The basic order of events should be as follows:

1. VI runs on Slave to configure it to accept a clock.

2. VI runs on Master to begin outputing the clock.

3. Master sends a signal to Slave to let it know that the clock is being generated.

4. Continue with the rest of your program.

Let me know if you have any questions about this.