Host-FPGA communication: Splitting DMA FIFO on FPGA vs. using several DMA FIFOs - which one is faster?

[okahilak]

I'm using FPGA (NI PXIe-7820R) in PXIe-1083 chassis, connected to the host PC via Thunderbolt.

My use case includes controlling several parallel processes on the FPGA from the host PC using a serialized message format, with the messages passed to the FPGA using FIFOs. Is it more, less, or equally efficient (latency- and throughput-wise) to set up a single DMA FIFO to communicate from the host PC to the FPGA and split the input messages for the parallel processes on the FPGA, compared to setting up several DMA FIFOs, one for each parallel process?

I'm particularly interested in the communication latency between the host PC and the FPGA. If I understand correctly, reading from several FIFOs in sequence would require random access to the host PC's memory: does that cause additional delays, compared to accessing a single FIFO, which seems to only require sequential access?

Are there other considerations when choosing one design over the other? I find it conceptually simpler for each parallel process to have its own FIFO, so I'm leaning towards that at the moment.

Thanks for the help!

[Terry_ALE]

For the scenarios mentioned I have observed performance to be the same.

I would go with a FIFO for each process due to the perceived simplicity.

[Terry_ALE]

There is host code optimization you apply by making a single set of code for handling a given process. Then call them reentrantly. As opposed to making copies of host code.

[okahilak]

Thanks for the quick reply! It's good to know that the performance will likely be the same or (at most) negligibly different when using separate FIFOs. I think I'll indeed go with that option, then. (I'm actually working with host software written in C++, so the host code optimization trick probably isn't applicable, but thanks for that anyway!)