I'm using a PXI 6683H - I am trying to generate a clock on a PFI terminal with a variable frequency.
I have used the "Generate Clock and Wait.vi" example to get started and successfully generated a fixed frequency clock. Good so far!
The problem is trying to vary the clock - according to the documentation, the niSync Create Clock seems to reserve the resources until the niSync Clear Clock is called. I have tried taking the example, connecting up Clear Clock followed by another Create Clock with a different frequency, but this doesn't work (the clock output simply terminates).
Perhaps I am using the wrong example, but can someone at least shove me in the right direction?
I have started looking at this a different way, by modifying the Generate Digital Pulse example but trying to wrap the central parts of the code in a loop, and calculating the delay time according to the desired output frequency.
This produces no output unless I move the VI for waiting for future events to clear out of the loop, in which case too many events are generated. I probably just need to slow the loop down, but not sure why that VI blocks things. Will upload this hacked example when I get back in to the office
Ok, attached a bodged up VI. This is just the example code with a loop in it.
Note that in the attached, I've tried hardwiring a constant pulse width and a frequency to see if that had any effect on performance issues (below) but it didn't.
What I've observed on the scope is that the pulse width is correctly reflected in the scope - so in the attached, I see 3ms width. But the gap between pulses is always too high, always offset by about 18 or 19ms. This means that if I demand 5Hz, I get ~4.5Hz. If I demand 10Hz, I get 8.3Hz, all the way up to 100Hz, where I get 50Hz.
I assume the code is introducing an overhead on the loop, but I'm not sure how to fix it and don't want to blindly fiddle with things.