12-06-2007 04:03 AM
12-10-2007 07:31 PM - edited 12-10-2007 07:40 PM
Hi,
Best Approach for the application in hand:
Now discussing the problem in application level, Frequency Response can be done even without using TCLK Synchronization. In this approach you would use two channels of the scope. Please refer to the picture below or Frequency Response.jpg in the zip file for hardware connections.
In this approach we will be splitting the signal and feeding one of them to Digitizer and the other one to DUT>> Digitizer. We can measure phase delay& Amplitude introduced by the DUT easily by using the reference signal connected directly to the Digitizer. The two channels of the Digitizer can be used to acquire the signal simultaneously. In this approach, clocks of Waveform Generator and Digitizer need not be synchronized and is easy to use.
Example posted in this link can be used for this application:
http://zone.ni.com/devzone/cda/epd/p/id/5079
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In regards to the questions posted in previous post:
I would definitely recommend using the example TCLK Synchronization attached to this post if you still want to use TCLK Synchronization approach
1) Why can't I select any Sampling Rate for this system?
When using TCLK Synchronization, the TCLK needs to find Highest Common Factor for the sample rates selected to produce an internal T-Clock. Refer to this website for more information on working of TCLK. http://zone.ni.com/devzone/cda/tut/p/id/3675
The error arises due to the selection of clocking mode as Automatic. There are two modes of CLoking on Waveform Generator: High-Resolution Clocking and Divide-by-Down Clocking Mode. Please refer to this webpage for more information on clocking. http://zone.ni.com/devzone/cda/tut/p/id/5535#toc5
For the sampling rates selected, the Arbitrary Waveform Generator might be using High-Resolution Clocking/DDS Mode to get clock rates closer to the values requested. For example requested sample rate on Digitizer might be 25MS/s and 15MS/s on Waveform Generator, the coereced smaple rate might be 14.9999998MS/s. The requested sample clock rate on Digitizer is 25MS/s. The TCLK might not find the Least Common Denominator.
If you select "Divide by Down" clocking explicitly on NI-FGEN for this application, sample rates will be coereced appropriately to use for TCLK Synchronization. However, this might not get close to the sampling rate required.
2) if I generate at the AWG a sinus with phase 0 then I observe at the Digitizer a phase that is not zero.
There are two things which are happening here.
a) The scope's fetching should be set "Relative to Start". This will enable the acquisition occur right after the TCLK Start rather than the immediate trigger which is the default case.
b) The Waveform Generator keeps generating DC signal at the last value for which the signal aborted. This means that when the digitizer acquires the last DC value still being generated by the Waveform Generator in the beginning of the record. To resolve this for the application, force the waveform to zero at the end or reset the device at the beginning of the NI-FGEN Session as shown in attached VI.
As discussed above the solution using two-channels of the scope is the best approach...
Please let me know if I am not clear on anything.
Thanks,
Kalyan
01-07-2008 10:02 AM
01-15-2008 10:07 AM