I'm using a Pxie-6548 which is connected to the CB/SCB-2162 thanks to a C68-C68-D4 cable.
I am doing an easy test, just generating from channels 25 to 30 and acquiring from channels 18 to 23 while the channels 25-30 are connected to channel 28-23 (acquisition and generation are synchronous) and sweeping the frequency. Then comparing the acquisition to the generation through " DWDT Digital to Digital Comparison.vi". I have no error in this configuration for all frequency measured (I have a 1MHz step).
Then I wanted to understand the effect of ExportedSampClk.Mode. I choose the "Delay" mode and give the value 0.2 to ExportedSampClk.Delay. Then doing the same test, I have now Failed Sample. I wasn't really expecting this, especially that I have failed samplefor different frequency but not all (see attachment). But maybe I'm wrong and this is normal..
If anybody understand this behaviour, could he explain it to me please. Or, do you have an idea what the problem might be?
Little precision, I use the exacte same length of cable for all connections (channels 18-23 to 25-30, Strobe to DDC Clk Out, PFI1 to PFI2), I use data active event which is supposed to eliminate the Round trip Delay (at least this is what I understand from http://zone.ni.com/reference/en-XX/help/370520J-01/hsdio/peliminating_rtd/ ).
I also found out that putting Noninverted to ExportedSampClk.Mode while still having the value of 0.2 to ExportedSampClk.Delay has the same behavior as putting delay to ExportedSampClk.Mode and having the value of 0.2 to ExportedSampClk.Delay.
But from the help of ExportedSampClk.Delay, it says "This property is relevant only when the Sample Clock Export Mode property is set to Delayed". Thus I shouldn't have the same behavior.. Does anybody has the same problem?
If not, could it be that there is a problem or a faulty device/software in my environment?
thanks in advance,
The reason you're seeing this kind of results is because you're actually modifiying the Data vs SampleClock relationship by playing with the Sample Clock Export Mode and Delay.
This documentation will explain the conditions and parameters you can use to properly phase align the SampleCock in respect to the Data you're sending.
Also you can look at the HSDIOs board specs, especially the Timing diagrams (both gen. and acq.)
You'll find there that the ExportedSampClk.Delay corresponds to the Tco=Exported Sample Clock Offset.
Hope all that will bring you sufficient informations.
Note: Concerning the ExportedSampClk.Mode "When the Sample clock rate is set to less than 25 MS/s, this property must not be set to Delayed".
Victor F. | Systems Engineer
Certified LabVIEW Developer | Certified TestStand Architect
National Instruments Budapest