A couple things to note - recompiling this design will expect a license from Xilinx for the SRIO to be present. Also, modifications of the SRIO IP will be in the Xilinx toolchain, and result in needing to modify VHDL that lives in our "Socketed CLIP" - this is an advanced skillset for some customers, but we do have partners in our network that can help make modifications to meet your exact needs if interested.
