Error -1074118135 PLL could not phase-lock to the external reference clock

[TimS.]

I've been trying to lock the PXI-5671 VSG to its Ref In source instead of the onboard clock and this is the following error that is received:

Error -1074118135 occurred at niRFSG Wait Until Settled.vi

Possible reason(s):

The upconverter reported the following error:

Measurements: PLL could not phase-lock to the external reference clock.

Make sure your reference clock is connected and that it is within the jitter and voltage specifications. Also, make sure the reference clock rate is correctly specified.

The clock source that I'm using is at the appropriate frequency (10 MHz) and levels (tried +6 dBm as well as +12 dBm). However, I have never been able to get the 5671 to lock to the Ref In as the clock source. Any thoughts?

I haven't dived into measuring the quality of the 10 MHz clock source that is being fed to the VSG but it is coming from a GPS Precision Timing Unit so I'm optimistic that the clock quality is within the tolerances of the VSG specs.

[Paul_C. · Accepted solution]

Hello tsileo,

The 5671 requires that you provide it a 10MHz square wave that is free-running at +/-0.5ppm accuracy. I believe the amplitude levels look correct.  I would confirm the accuracy of your GPS unit's clock.  I would also ensure that the free-running clock is provided prior to starting the NI-RFSG task.  Depending on the chassis you are using, you might be able to try connecting the chassis 10MHz clock to the REF in connector just to ensure that there isn't something wrong with the device.  

Regards,

Paul C.

[TimS.]

Hi Paul,

Thanks for the info. I guess I missed the part about the 10 MHz ref needing to be a square wave in the specs. After providing the 5671 a 10 MHz square wave everything worked as expected.

Thanks,

Tim S.