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Does "IO Module\Reinitialize" FPGA I/O NODE reset my block memory to default (as set on project explorer)

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I would like to reset my block memory to all zeros (only once) when the FPGA code is run. In my past experiences, this was not done by the "IO Module\Initialization Done"  FPGA I/O NODE.  To alleviate this, I used a SCTL which runs through each address of the block memory and stores a zero. The approach works great, but I would like to save some space since we will be quadrupling the size of the code in a couple of months.


FPGA: 7954r

IO Module: 5761r


Thanks for looking!



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Accepted by topic author Denn_Mann

Hey Denn_Mann,


You should be able to set your memory to initialize to zero in the Memory Properties. Here is a link that should help you out:




Hope This Helps,


Doug B

Applications Engineer
National Instruments
Message 2 of 4

Hi Doug,


I had tried that in the past and didn't get it to work.  I guess I must have forgot to press "Apply."  It is now working.


Thank you so much for your help!



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Message 3 of 4

No problem, glad everything is up and running for you.

Applications Engineer
National Instruments
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