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DSA disciplined sample clock timebase from PXI-6653 and PXI-6682

Hello,

 

I would like to get some guidelines regarding this issue from people who work a little on timing and synchronization aspects in LabVIEW.

 

I have few PXI-1033 chassis with PXI-6653, PXI-6682, PXI-4472 and PXI-4495. I would like to synchronize both chassis in the following way:

 - Each PXI-1033 are situated far from each other.

 - PXI-6682 will trigger according to the GPS timestamp and will provide PPS signal to PXI-6653.

 - PXI-6653 will provide reference clock timebase to DDS input in DSAs.

 - PXI-4472 and PXI-4495 will have and the same timebase in all different chassis.

 

In the NI DSA Usra Manual under Timing and Synchronization I can see that there are two ways of synchronization configuration:

 - Reference Clock Synchronization,

 - Master Sample Clock Timebase Synchronization.

Which of these should I use? I will have PXI-4472 and PXI-4495 in two different chassis.

 

I know right now how to configure the DSAs using DAQmx and how to trigger DSAs using niSync however it is of great unknown how to route the signals between PXI-6682 and PXI-6653 and how to send the timebase from PXI-6653 to DSAs via backplane.

 

Any help would be strongly appreciated. I can see that this configuration would be interesting for many applications, so looking forward to have nice discussion about it.

 

Best regards,

--

Łukasz

 

 

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Hi,

You can use the PXI-6682 and PXI-6653 in combination with each other to discipline the PXI_Clk10 of each PXI-1033 chassis to GPS.  By doing so, each chassis's PXI_Clk10 will be phase locked and aligned (plus or minus some error in the order of nano-seconds).  This will enable you to use the Reference Clock synchronization described in the NI DSA User Manual because the all the chassis' PXI-Clk10s will be synchronized together.


As for a few details when getting started with clock disciplining...

1. Make sure that the routing an external clock to peripheral slots feature is enabled on the PXI-1033.  A switch on the backplane of the chassis controls this feature (for more details refer to Chapter 1 Getting Started»NI PXI-1033 Backplane Overview»System Reference Clock section in the NI PXI-1033 User Manual).
2. Next, place the PXI-6653 in the system timing slot.  Once the clock disciplining software is running, this module will route its 10Mhz clock (which will be disciplined to GPS) to PXI_Clk10.  PXI_Clk10 is then sent to every slot via the backplane.
3. The rest of the modules can be placed in the available slots.


NI PXI_Clk10 Disciplining for PXI Links:
    User Manual
    Software Download


I hope this helps.

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Hi TylerK,

 

Thank you for your fast reply.

 

I also had a small chat about it with NI support and they also suggest to use the 'Multi-device PXI_Clk10 Disciplining 1.1' software. The API provided in the bundle can start, finish and check status of the disciplined clock.

 

As also Jared mentioned here there is no possibility to synchronize PXI-4495 and PXI-4472 in the same chassis. Fortunately I will not need that. However I will need to check if both DSAs can be managed by the 'Multi-device PXI_Clk10 Disciplining 1.1' software. Do you have any experience with that?

 

The table below shows what is it about. It can be found in the DSA manual.


Configuration

Reference Clock
(PXI/PXIe Only)

Master Sample Clock
Timebase*,†

NI 449x and NI 449x

Supported

NI 446x and NI 446x

Supported

Supported

NI 447x and NI 447x

Supported

NI 449x and NI 446x

Supported

NI 449x and NI 447x

NI 446x and NI 447x‡, **

Supported

NI 449x and NI 433x††

Supported

* DSA devices with an eHM (PXI hybrid compatible) backplane connector do not support master sample clock timebase synchronization.

† When using master sample clock timebase synchronization in a PXIe chassis, all DSA devices must be slaves. A timing module capable of driving the PXI Star and trigger lines must be the master.

‡ Multirate synchronization is not supported.
** The NI 446x must be the master DSA device.
††
NI-DAQmx 9.1 and later support synchronizing NI PXIe-4330/4331 bridge devices with NI PXIe-449x
devices using reference clock synchronization. The NI PXIe-4330/4331 must be the master device.

Note
: NI USB-443x devices do not support synchronization.

 

There are also other issues with the synchronization related with anti-aliasing filter delay in DSAs. If someone would have any ideas how this can compensated in PXI-4495 and PXI-4472 using DAQmx please write in few sentences. I will have the same sample rate in all of DAQs however it would be also good to adjust the delay compensation depending on sample rate.

 

Another issue it with the software delays if the system is not using real-time operating systems but some non-deterministic such Windows is. Will this introduce significant uncertainties? How about the triggering, how to do this in order to reduce as much as possible software delays?

 

Thanks!

--

Łukasz

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Message 3 of 11
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Hi,

 

Most of my expertise is with the NI-Sync software and hardware, and I am not as familiar with the DSA modules. 

 

To answer your question about triggers and determinism, you can use the PXI-6682 to generate a start trigger based on GPS time.  Using NI-Sync, you can create future time events (which are hardware triggers that occur at an arbitrary future time) to start the data acquisitions.  These events can be scheduled with 10ns of resolution and consecutive events can occur within 50ns of each other.  Also, these events are synchronized to the PXI-6682’s time base.  By using the Multi-device PXI-Clk10 Disciplining, your board’s time base will be synchronized to GPS.

 

Regards,

 

-Tyler

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Hi Tyler,

 

Thank you for the reply.

 

At this stage I did manage with significant help from NI Engineers to configure two systems based on PXI-1033 with PXI-6682, PXI-6653 and PXI-4472. PXI-4472 is synchronized by sharing the oversample clock over the backplane PXI star trigger lines. The PXI-4472 module is directly using the (over)sample clock generated by DDS in PXI-6553 OXCO.

 

Everything looks nice however after many tests I cannot synchronize two chassis. I simply see that the clocks drift freely even if the self-survey is done, there are at least 4 satellites available and the phase is locked. Do you have any ideas where the system can be improved?

 

Regards,

--

Łukasz

 

http://lukasz.kocewiak.eu

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Message 5 of 11
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Hi,


I have a couple of questions for clarification. What is phase locked?  Which clocks are drifting and by how much?


As for the PXI-6683’s DDS, it derives its frequency from PXI_Clk10.  If the chassis PXI_Clk10s are synchronized, the DDSs will be synchronized (phase locked if generating the same frequency).  With the Multi-Chassis PXI_Clk10 Disciplining software running, both chassis’ PXI_Clk10s should stay aligned to each other.  They may drift a few nano-seconds from each other, but they should never run away from each other.  If the PXI_Clk10s are running away from each other, then most likely the chassis are using the backplane’s oscillator for PXI_Clk10 and not the PXI-6683’s OCXO.  If you see this issue, check the switch that controls the source of PXI_Clk10 on the backplane of each PXI-1033. 

 

One other thought, are you waiting for both servos to lock (Get Clock Servo Status.vi) before you begin your data acquisition?


Regards,


-Tyler

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Hi Tyler,

 

Thanks for the reply. I explains a little.

 

I was not sure if I had to wain of both servos should be locked or I simply should only run the application in the background. During the tests I did manage to lock servo in one of the chassis (see figure below). However even after many hours I was not able to lock the servo in another chassis. Based on what you are saying it is crucial to have both servos locked. I read that this can be affected by not stabilized oscillators but how long should I wait for that, a day? Do you have any ideas how to speed it up?

ClockDiscipling.png

 

During data acquisition I can see that PXI_Clk10 is present and the DDS is generated on PXI-6653. I do not know how to check if PXI-1033 is using the backplane oscillator instead of the oscillator from PXI-6653. I also do not see any switch that controls the source of PXI-Clk10 on the backplane. Is it outside or inside the chassis. Outside I can see only one switch to control fan rpms.

 

Here you have some exemplary results. As you can see in time the DSAs can significantly drift. I used 102.400kS/s/ch during the test. Measurements are triggered using absolute GPS timestamp from PXI-6682.

Sync1-Kocewiak.png 

Figure 1  Test#7: Switching operation.

 Sync2-Kocewiak.png  Sync3-Kocewiak.png

(a)

(b)

Figure 2  Test#7: Synchronization mismatch, (a) voltage disconnection, (b) second grid voltage connection.

 

Regards,

--

Łukasz

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Message 7 of 11
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Hi,

 

I took a picture of the PXI-1033 backplane and circled in red the switch that controls the source of PXI_Clk10.  The switch is actually a jumper.  The picture below shows the backplane configured to use its oscillator for PXI_Clk10. If the jumper is moved up, the backplane will use the module in slot 2 for PXI_Clk10.

 

PXI-1033 Backplane Switch.jpg

 

As for the servos, they should be locked within 100 seconds or so.

 

Regards,

 

-Tyler

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Hi Tyler,

 

Thank you for that.

 

I did some test today at home (this is the only place where I can put GPS antennas at the top of the roof) and actually I am quite satisfied about the results.

 Sync4-Kocewiak.png  Sync5-Kocewiak.png

(a)

(b)

It seems that it actually works. I still need to optimize the software and perform long-term test. However I am quite optimistic.

 

Please note that the test is done with the sample rate of 102.4kS/s and until now I have tested the system with PXI-4472. As far as I can see the problem was with the PXI_Clk10. I had to change the jumper in PXI-1033 in order to take the PXI_Clk10 from Slot 2 instead of backplane.

 

Best regards,

--

Łukasz

 

http://lukasz.kocewiak.eu

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Hi All,

 

Here is small update.

 

I did manage to run the software with PXI-4472 and PXI-4495. Firstly I did it without the anti-aliasing filter delay as it can be seen below. As you can see the delay is all the time constant and is equal to 24 samples. I used in this case sample rate of 44100 S/s/ch.

 

 Kocewiak-Disciplined-Clock-01.png  Kocewiak-Disciplined-Clock-02.png

(a)

(b)

 Kocewiak-Disciplined-Clock-03.png  Kocewiak-Disciplined-Clock-04.png

(c)

(d)

 

Later I also implemented filter delay compensation. Fortunately for PXI-4495 it is by default supported by DAQmx. However for PXI-4472 it is not supported and unfortunately for 44.1kS/s the delay is not an integer number (37.7 samples according to NI 447x Specification). Due to this fact I have always this one sample delay. I think that it works right now.

 

 Kocewiak-Disciplined-Clock-05.png  Kocewiak-Disciplined-Clock-06.png

(a)

(b)

 Kocewiak-Disciplined-Clock-07.png  

(c)

 

 

I have two issues/questions:

- Does the driver DAQmx for PXI-4495 compensate precisely the filter delay or is it rounded to the nearest sample? I am wondering if during data post-processing I only need to think about interpolation for PXI-4472. Is there any way actually to apply trigger delay of non-integer value? Right now I use 39 samples for 38.7 filter delay.

- I also have PXI-6133 and I would like to use the same synchronization for the max sample rate which is 2.5MS/s/ch. Is it possible also to route the disciplined clock to that board? Can this be taken directly from PXI-6653 (like in PXI-4472) or should it be once again disciplined (like in PXI-4495)?

 

--

Łukasz

 

www.lukasz.kocewiak.eu

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