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Compilation problem in PXIe-7695R FlexRIO

Hello,

 

I am new to LabVIEW FPGA, before this, i used to do FPGA's in VHDL using ISE suite. In that process, I just need to change the bit files from iMPACT and my FPGA runs with the new bit file. but I am trying to do the same thing here and facing problem as described below;

 

So i've created two projects, both with different names and in different locations. Both of the projects are nearly similar (simple DMA FIFO), except the "maximum number of elements" (of DMA FIFO) is different (one contatains 1023 and other contains 4096). Now i am compiling the first project (with 1023), it gives me a bit file and runs on the FlexRIO.

Now i've compiled the second project (with 4096), got its bit file and runs on FlexRIO.

 

Both of the bit files are located in different locations. Now at this point, when i open my first project, it again asks me to compile. why is that so ? for rechecking, I reloaded my FPGA target with that specific bit file, but still i need to compile. Am i doing some sort of mistake here ?

please help, as this hurdle waste allot of time of mine in compiling again and again.

 

 

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Hi Sheraz,

 

When you open the reference to the FPGA code using Open FPGA VI Reference.vi, do you have it configured to reference the VI or the bitfile?

 

If you have it configured to reference the VI, I'd suggest changing the configuration to reference the bitfile instead. 

 

If you're not familiar with how to do this, more information is available the FPGA Module Help under the Configure Open FPGA VI Reference Dialog Box topic.

 

If this doesn't work, or you're already doing this, please let us know and we'll continue to troubleshoot as necessary.

 

Thanks and regards,

Dave C.

Applications Engineer
National Instruments
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Thanks Dave for your responce 🙂

 

I've taken ur suggestion into consideration, but inface, i've already tried that. selected an appropriate bit file by usign open FPGA VI reference.

However, I came up with a solution, I copied the same project in different location, and changed the name of the Project, the VI files and the FIFO's, then updated the code with the new fifo. This solved my problem.

Now I can use both bit files to be burned on the FPGA, without any re-compilation. 🙂 

 

Regards

Anum Sheraz

 

 

 

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