Acq_Regional_Clk Error - 1 Gbps Sampling with PXIe 6587

[Dr_Ian_Mc]

Hello out there,

I have been trying to configure for 1 Gbps sampling for two weeks to no avail. FPGA training course has helped me write better FPGA code, but I still have the same problem whenever I try to use the Acq_Regional_Clk. Simulation works fine, compile goes fine, but then upon loading to the FPGA I get the following error:

"LabVIEW FPGA reported the following error:

An error was detected in the communication between the host computer and the FPGA target.

If you are using any external clocks, make sure they are connected and within the supported specifications. Also, verify that the rate of any external clocks match the specified clock rates. If you are generating your clocks internally, please contact National Instruments Technical Support."

System Description: PXIe 1071 Chassis, (slot 1) 8100 controller, (slot 2) 7961R FlexRIO FPGA, (slot 2 adapter) 6587, (slot 3) 6341 DAQ.

Description of the attached code: I was originally trying to actually read the LVDS DIO, but then realized I got the same error for simply creating a loop running on the Acq_Regional_Clk. To test if I can use the clock, I have two loops running, a quick and a slow, and I try to pass some data between the two with some FIFOs. There are two versions of this vi, one where the quick loop uses the Acq_Regional_Clk, and a control vi that simply uses the 200Hz clock. Both run correctly in simulation, and the 200Hz version runs perfectly on the hardware. The Acq version, however, errors as described above. In case it was a problem with running in interactive mode, there are pairs of host vis (for both the Real-Time target PXIe chassis and the PC). They experience identical symptoms.

Section of the code

Please help if you have ideas. I'm reaching the extent of my creative troubleshooting.

Thank you in advance.