About Reference clock in PXIe

[beihang university]

I have read about PCI Express reference clock in CPCI Express spec. & PXI Exprss spec.

But i still have questions about it.

Firstly, it is said that  reference clock is optional for PCI Express endpoint boards, is that correct? What is reference clock used for? Which role does it play?

Secondly, can i use an on-board chip to generate the 100M HCSL refclk instead of the refclk from backplane for my CPCI/PCI Express board?

thanks very much!

[Robert__R]

The PCIe reference clock is used, among other things, to ensure that devices are transmitting data at a rate that the link partner can receive.  The devices generally use it to help recover the clock and data as well.  

You need to use it except in specific cases.  You can use independent clocks on the two sides of the link when both sides are using non-SSC clocks, but you don't usually control the host clock, so this is rarely the case.  Otherwise you need special support in the devices, which you're unlikely to get.

So the short answer is that you should use RefClk from the backplane.

Robert