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PXI
AC coupling for FPGA module
Solved!
Hi @shou14,
I don't have access to your example project at the moment, but I'm guessing that AC coupling might be enabled by default and it just hasn't been set in the example.
I do know that the FlexRIO Instrument Development Library (FIDL) has an interface for you to set the coupling programatically: http://forums.ni.com/t5/NI-Labs-Toolkits/NI-FlexRIO-Development-Tools/ta-p/3517734
Hey Steve! FIDL is a handy resource, but we might be able to get away with a pretty quick modification to your FPGA code to put the analog front end in DC coupled mode. I'd recommend taking a look at the NI 5734 CLIP Help that is installed with the FlexRIO Driver. You can find it by opening LabVIEW Help and searching for "5734." The CLIP help describes all of the I/O signals available in LabVIEW FPGA, including the right signals and values to use to put the I/O module into DC coupled mode.
You will need to write a few signals in the "Configuration Loop" in your top level FPGA VI block diagram. I'm not 100% sure, but I believe it has to be done for each ADC channel. You would write a "3" for "User Command," "ADC#" for "User Data 0," a "1" for "User Data 1," repeat for each ADC#, and then wait for IO module Initialization Done like in the original example:
Would somebody be able to add a little more detail to the comment about the code that is needed in the top level VI on the FPGA target in the configuration loop? Currently, this is the code I have in the configuration loop,
I have this code deployed on the FPGA target of a slightly expanded "NI 5734 getting started example". However, when I run an acquisition for channel 0, while providing a square wave into channel 0, I get the following input. Here, the top graph is the raw data and the bottom graph in the scaled data coming from the NI 5734:
As can be seen, channel 0 is still collecting data in AC mode. I have also tried to update the coupling mode using the format given in the "changing clocks NI 5734 example" without success.
Any help or suggestions would be greatly appreciated.
All the best,
Austin.
It seems to me that you should configure the IO and then use a loop to check to see if it is done initializing before doing anything else.
I am still having trouble changing the AC coupling mode to DC. As nobody else on the forums seems to be having this much trouble maybe I am doing something simple wrong. It seems others (https://forums.ni.com/t5/PXI/NI-5734-Hardware-Problem/td-p/1939391) have had success using the example code "NI5734 - Clock Select (FPGA)" to change the AC coupling, but I am unable to get this to work. This could be related to an error I get on compile, but for completeness, I will show what I am doing in hopes someone will see an error or be able to provide me with code that works on their setup. My intention with this code was to be as simple as possible and as such, I am just returning values to the host VI to plot in a chart.
For starters, here is my project,
And here is the code running on my target (NI 7965R). My main understanding is that I use the loop on the bottom to create links to the I/O adapter so I can set my user-controlled variables.
Next is the VI I run on the host. (This is a Windows 7 machine, I do not have any real-time interface). My only goal with this code is to set the AC coupling to DC and collect some data. The sub VI should take care of setting the AC coupling mode. The inputs are user command =3, user data 0 = 0 and user data 1 = 1, or in my understanding, set channel 0, coupling to DC.
Here are the contents of the sub VI code. I gleaned this code from this link (https://forums.ni.com/t5/LabVIEW/Changing-GAIN-on-NI-5734-ADC-introduces-noise-ripples/td-p/2928098) but this is the same code as the set clock example, so my understanding is it should work. (Of course, it may not as I am still unable to change the AC coupling to DC.)
Lastly, when I compile the FPGA target I get the following error at the end of my complaining. However, as seen in the post above I can still get data from the NI 7965R card so I don't know if this error matters but maybe it is the reason I can not set my AC coupling. (I am not trying to run off of any external clocks, I believe I am compiled on the 40 Hz default clock and I only use the sample clock for taking data).
Other than what I have here I believe I am running the standard 40 MHz clock for my code. I have had some odd issues when trying to set/configure the VI used in the "open FPGA VI reference", Do I need to select the "dynamic mode" or the "Bind FPGA host reference to type definition"? I noticed the change clock example uses the latter ("Bind FPGA host reference to type definition") but if I do this I am unable to connect my wires for FPGA VI reference to the other functions.
In the case that it helps I have also attached my VIs to this post.
Tanks in advance for any help,
Austin.
I was able to get it working. Here is code that should help others.
After much searching and deep within the FIDL library I was able to find some code that worked on my system. I think it had to do with how the commit booleans were set. For those interested, here is the code I used to set the DC coupling to AC (only for channel 1). I have also attached the host and target codes to this post.
