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6682 1588 synchronisation

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I'm trying to synchronize two PXI chassis with 1588 clocks. To achieve this i use 2 PXI 6682H boards.


I created a test program which:

- init the 1588 (init the clock, set time reference , start the participation in the 1588 network)

- wait to be synchronized (only the slave)

- create the clock at a round second.


The 2 clocks are synchronized (+/- 10 ns) but the problem is the phase ( 0 -750 ns). I watched the 2 clock with a scope and if i run severeal time the same program i have a phase error wich vary from 0 to 750 ns. The clock frequency is 1,5 MHz.


I don't understand , normally when i create the clock, the two clocks are synchronized, however i can have 750 ns error ...


Any idea welcome ...

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Accepted by kabooom



There are a couple of things that I can think of that could result in the behavior like what you are seeing


The first is if the clock generation was started before the slave had made its initial timekeeper adjustment to match the master.  It is easy to verify if this is the problem: when you see frequency-locked, but out-of-phase clocks, can you stop clock generation and re-start it?  Do you see the same offset?  Of course, when stopping-re-starting clock generation, 1588 operation should not be interrupted (use the "niSync Create Clock" and "niSync Clear Clock" VIs).


Another thing that could cause this is if the start time for each clock is in a different second's boundary.  Since the period of a 1.5MHz clock is such that you don't have a whole number of periods within a second, if you start clk A at time 9:00:00 and clk B at time 9:00:01, the clocks will have an offset.  Additionally, the PXI-6682 can only generate clocks with periods that are a multiple of 10ns.  The period of a 1.5MHz clock is 666.6666... ns.  The NI Sync driver will round this up to 670ns, so the offset of clocks started at different times can be as high as half of that (335ns).


I know this would not explain the larger (up to 750ns) offsets you have seen, but I hope this can help in finding the issue.





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Hi Alejandro ...


Thansk a lot for your help ...  As you wrote the problem was the frequency of the clock : the period of a 1.5MHz clock is such that you don't have a whole number of periods within a second.. I don't know why i didnt think about this earlier. I tryed the same code with 1 Mhz Frequency and the two clock are synchronized !!!! 


Again thanks a lot !


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I am glad we were able to figure out the problem.  Remember, I am pretty sure that if you schedule the start time of both clocks to be the same time, even the 1.5MHz clock would be synchronized.





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Yes, you're right, the problem is in our case, we have for example 4 chassis wich are runing and synchronized to make a test. During this test, we want to be able to start a 5th chassis that must be automatically synchronized with the other 4 already started...


That's why i can't start all clock at the same time ...

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