10 MHz ref CLK in pxie 5170 module

[meh1011]

Hello 

I want to use pxie 10MHz CLK in my FPGA code as IO port, but this CLK isn't accessible. what should I do to accessing this CLK?   

[crossrulz]

In the project, you should be able to right-click on the FPGA Target and add IO.  The PXIe reference clock should be in the list of available IO.

[meh1011]

thank you crossrulz 

I checked that list but there wasn't 10MHz reference CLK. 

[crossrulz]

With PXIe, you might only have access to the 100MHz clock (have not had to do this with a PXIe yet).  Would that work for you?

[meh1011]

I want to use pxie ref CLK for synchronization, I didn't find pxie CLK 10 , so when I want to use CLK 100 in generating intermediate file step, it has an error:

" An internal software error has occurred. Please contact National Instruments technical support at ni.com/support with the following information:

Error 7 occurred at Read from Text File in niFpgaCodeGeneration_GetBuildResultsXML.vi->niFpgaErrorDialog_ReadErrorData.vi->niFpgaGenerateCode_ErrorDialog.vi

Possible reason(s):

LabVIEW: File not found. The file might be in a different location or deleted. Use the command prompt or the file explorer to verify that the path is correct.

C:\NIFPGA\compilation\test_PXIe-5170R(8CH)_StreamToHost(FPG_Q4sbNjgPnqI\BuildResults.lvtxt"