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Does Your Company Incorporate PCB Footprint and Land Pattern Standards?

NatashaB
NI Employee (retired)

How does your design team select the land patterns and footprints used in your designs? Is it simply a matter of selecting one from your CAD database that best matches the package dimensions from the datasheet, or is your company at the other end of the spectrum maintaining a cross-company database of approved IPC-compliant land patterns?

When designing a PCB, it is essential that the conductive lands (often referred to as footprints or land patterns) used in your layout are accurate to ensure proper solder joint connections when the board is manufactured. Often designers will simply choose a land pattern that best matches the package dimensions in the datasheet, but is this a reliable methodology? Furthermore, although datasheets will often specify that package dimensions conform to a packaging standard (such as JEDEC), there is often some variance. Can you be confident that a generic SOIC-14 land pattern from your CAD library will be appropriate for both an Analog Devices package and a Texas Instruments package of this type?

It gets even more complicated if you need to account for environmental or form factor limitations in your design. If you are designing in a particularly harsh environment for example, physically rugged connections will be necessary and oversizing of land pattern dimensions will be required. Conversely, if you are designing an extremely dense board, for example a mobile-device, you will want to make efficient use of your space by undersizing pad dimensions where possible (especially if you are designing a low-current device). How can you be sure that you have fully optimized the layout of your board, while at the same time have maintained proper solder joint connections?

And further downstream, perhaps the circuit boards are being sent to an assembly shop that makes use of an automated pick-and-place machine. In this case, it's important that the default orientation of the land patterns are in accordance with industry-standards to ensure that the rotation specified in the Parts Centroid file is accurate. And let's not forget best practices in surface mount layout - pin 1 indicators, fiducials, reference designators, silkscreen placement (which can affect solder joint connections if it overlaps conductive lands). What exactly are these best practices, and how should they be incorporated into the land patterns used in your designs?

The IPC has stepped in to resolve some of these questions with the IPC-7351 Generic Requirements for Surface Mount Design and Land Pattern Standard. The standard, based upon well-researched mathematical formulae, accounts for fabrication, assembly, and component tolerance to determine land sizing. The standard provides a 3-tiered density system (most when rugged physical connections are required, nominal and least for optimizing area constraints), solder joint analysis specifications, zero component rotation to ensure proper pick-and place automation, and a unique land pattern naming convention that provides a means of managing land pattern variants.

IPC-compliant land patterns were first introduced into Ultiboard 10, and have been added steadily since this release. The latest version, Ultiboard 11, introduces over 1500 additional IPC-compliant land patterns. These land patterns include a wide variety of integrated circuit and discrete packages (RLCs, transistors, diodes, crystals, etc.). More information on these new land patterns can be found here.

More Resources:

  1. IPC Website
  2. Learn More About Multisim and Ultiboard for Rapid Design, Simulation and Prototyping
  3. Download Multisim and Ultiboard 11
  4. Standard to IPC Lookup Table

Natasha Baker
R&D Engineer
National Instruments

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