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OK, got it all build....

Had some serious problems with the package builder. It seems selecting the destination to "Project Templates" does not stick. Every time I save an re-open the package specifications, the destination is reset to vi.lib again.

Is this a known bug (running the newest VIPM 2014.0.0.1941).

EDIT: further investigating this: The setting does not stick if I select it from the "destinations" listbox. It works correctly if I instead select the right path from the "Base Path" ring to the right of it.

Like others have experienced, I cannot successfully run without it wanting to recompile the FPGA after opening the newly created sample project. The bitfile is included in the project, not sure how to fix this.

Is there a way so the project comes up with the myRIO-1900 tree expanded so RT Main.vi is immediately visible?

I will submit "as is" and try to fix these things during the review process.


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Re: OK, got it all build....

It seems the project expects a different bitfile name than what's included with the build. Somehow it expects a bitfile name that starts with a name that contains the project name selected by the user.


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Re: OK, got it all build....

altenbach wrote:

It seems the project expects a different bitfile name than what's included with the build. Somehow it expects a bitfile name that starts with a name that contains the project name selected by the user.

Did you have the MetaData.xml file HidePrefix tag set to "true"?  When I open the newly created project the bitfile is there and it has the correct name and the node that opens the FPGA Reference is pointing to the FPGA bit file. The only thing I can think of that would rename the files in the project is if when creating the project the user had the option of adding a prefix.

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Re: OK, got it all build....

altenbach wrote:

Had some serious problems with the package builder. It seems selecting the destination to "Project Templates" does not stick. Every time I save an re-open the package specifications, the destination is reset to vi.lib again.

Is this a known bug (running the newest VIPM 2014.0.0.1941).

EDIT: further investigating this: The setting does not stick if I select it from the "destinations" listbox. It works correctly if I instead select the right path from the "Base Path" ring to the right of it.

Just making sure we are talking about the same thing, the Destinations section only points to where the different Destinations point at and can be left with the default values:

Destinations.PNG

In the "Source File Settings" is where you need to set your project to have as a "Destination" from the dropdown box "Project Templates"

Source Settings.PNG

This one did stick every time we tried to build a new package today.

I hope this helps.

Fab

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Re: OK, got it all build....

VIPMBugger.png

I am talking exclusively about the Destinations page in the above picture:

There are two places where we can pick the destination: A and B.

Changing A updates B. If we change at A, the change is lost. If we change at B, the change sticks.

If I select a destination in A, B gets also updated, but the packet spec is not marked dirty and the change gets lost. The build is not marked as dirty if this is the only change. If we save and re-open, we are back at the old defaults.

If I now change B back to  to something else (needed else we don't get a value change at B because we select what it already is) and now select the correct destination with the ring at B again, the change sticks. The build is marked dirty in the window title (*).

Nah, works correctly (misunderstood the function of this page)

I'll look into the xml options.


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Re: OK, got it all build....

FabiolaDelaCueva wrote:

Did you have the MetaData.xml file HidePrefix tag set to "true"?  When I open the newly created project the bitfile is there and it has the correct name and the node that opens the FPGA Reference is pointing to the FPGA bit file. The only thing I can think of that would rename the files in the project is if when creating the project the user had the option of adding a prefix.

Yes, it is set to TRUE. Is this the correct setting?

If I open the template, It asks me to name the new project. Whatever I chose there gets propagated to the expected bitfile.

Here is what I see (I name the project "voc008" for simplicity. If I open the FPGA build spec, it tries to find a bitfile that starts with "voc008..." instead of what's already there.

bitfileScramble.png


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