I have now finished my code and I'm trying to build my package. Whenever I try to build my package with VI Package Manager, I get error 74. I have read the documentation on both the following links:
I have also read the common error causes on the JKI website. After reading all this, I modified my RT code to include the conditional diagram disable structures as indicated. I don't have any FPGA VIs to worry about. I have the most recent version of VIPM.
I have also followed all the instructions in this link to build the package:
After pulling pieces out of my code, I have found that the only way to get rid of the error is to pull out my VI that has references to the myRIO driver. Even if I just put the open and close VIs into my project and then build it, it will get error 74.
Any ideas what I might be doing wrong?
The first link you referenced contains a further link to the JKI site with a fix for this issue.
Using an Open FPGA Reference to a bitfile instead of an FPGA VI can result in Error 74. There is a workaround documented here: Error 74 - Open FPGA Ref with .bit File and this issue is fixed in VIPM 2014.
Thanks for replying so quickly!
I did notice that link earlier, but I ignored it since I am not using the FPGA Open/Close Reference function in my code. What I did not realize at the time is that the NI-RIO driver functions use those VIs. I have now followed the solution in the above link, and been able to successfully build my app. Thanks for your help Christian_L!