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"Digital Output Loop Shutdown" without any DAQ Error

Hello,

I have a RT controller and CDAQ is attached to it. I have my SDF with all DO in NI 9403 is populated. I have a model developed in LabVIEW which have a square wave generator which is mapped to DO through mapping tool. (basically am switching the relay ON and OFF with different speed).

 

But the issue, the Veristand is shutting the DO output loop without having any DAQ error (its printed in the console and no veristand error message). DAQ loop rate set is 500Hz. Could you please help me on this, why this is happening?

 

Thanks,

Rajesh

Rajesh Raghavan Nair

Certified LabVIEW Architect
Certified Teststand Architect
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Hi Rajesh,

 

What specific RT controller and cDAQ are you using? Can you post your SDF so that we can see how everything is configured?

 

I don't believe that cDAQ chassis can be used with VeriStand. Are you sure you aren't using a cRIO or an ethernet expansion chassis?

 

Regards,

 

Jordan Calvert 

 

 

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Hello  Jordan,

 

Thanks for the reply. the RT controller with Pharlap is PXIe-8840 and the CDAQ which is plugged into RT with USB is cDAQ-9171. In cDAQ 9171 1 NI 9403 card is inserted.

In MAX controller is showing CDAQ and I was able to switch the DO. The issue is happening after few minutes of switching may be after 15 to 20min.

Attaching the SDF.

 

Regards,

Rajesh

Rajesh Raghavan Nair

Certified LabVIEW Architect
Certified Teststand Architect
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Hi Rajesh,

 

I was able to set up a similar system to output digital signals from a LabVIEW model to a DO module in a cDAQ plugged into my RT controller. I was able to get my system running, but I haven't seen my DAQ IO loop stopping after leaving the system running several hours.

 

Can you try monitoring the DAQ Error system channel? In your SDF I see that you are filtering out DAQ errors, so there is likely a DAQ error occurring but it is not stopping the execution of your project and reporting the error because filtering is enabled. Even with DAQ error filtering enabled, the DAQ Error system channel will show us any DAQ faults.

 

Jordan

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Hello Jordan,

 

I monitored DAQ error channel and it was not showing any error. I tried both ways disabling and enabling the DAQ filter error and also i tried to reduce the speed of DAQ loop.

 

I just want to point out that my model is mapped to this enumerated DO channel and my model will switch the DO channel ON and OFF at max speed of 10hz(as of now)

 

Please let me know your thoughts.

 

Regards,
Rajesh

Rajesh Raghavan Nair

Certified LabVIEW Architect
Certified Teststand Architect
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Rajesh,

 

How do you know that the DIO loop is stopping? Do you just see that the modules stops switching its output value? Does it always stop outputting after the same amount of time?

 

Do you see any other VeriStand errors in any of the error channels? 

 

Jordan

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Jordan,

 

Initially I was also wondering whats happening. Because there is no error in Veristand or in system error channels. I noticed the issue when I stops hearing the relay switching. Then I verified the model and Veristand channel and its keep on updating. If I plot that channels I am able to see the switching in intended freq.

Then I look in RT console and when its happening RT is printing "Digital Output Loop Shutting down". No timing is random.

Till now I can't figure out whats happening. I can attach the model vi so that may be you can recreate the issue.

 

Thanks!

Rajesh Raghavan Nair

Certified LabVIEW Architect
Certified Teststand Architect
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Rajesh,

 

Are you getting any late counts of the Primary Control Loop? Also, can you try creating a new SDF that just contains the model and the single digital output line you want to write to?

 

Jordan

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No there is not late counts. I will try that.

 

One more thing I noticed, when this problem happens the DO loop is not shutting down during undeployment( in this case it didn't shutdown, i think it went to some undefined state). The veristand has to do force shutdown.

 

Thanks

Rajesh Raghavan Nair

Certified LabVIEW Architect
Certified Teststand Architect
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