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What determines the upper limit for the PCL rate?

Hello,

 

I want to run a 10 kHz PCL at PXIe-8880. I also need to use 480 I/O on the PXI. And when I start to add Veristand channels for these I/O, first HP Loop duration exceeds 100uS and my PCL rate goes to 5 kHz and if I continue to add channels then it goes to 3.333 kHz. When these events take place, the core running the PCL goes from 98% to 54% and then 32%. 

 

I am wondering if the only limiting factor for PCL rate is the Veristand channel count in my case or is there anything I can do to solve this problem?

 

Thanks

 

I have a PXIe-1085 chassis with PXIe-8880 on.

Modules are:

 

2 x PXIe-6365

2 x PXIe-6739

2 x Pickering 40-412-111

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