I'm attempting to use a labview model to take over a couple of calculated channels that are currently in one of my veristand projects. Without the LV model, it works just fine. But after importing the model and hooking up all the necessary inputs and outputs, it wont' deploy. Gives Error -307703 when deploying. More info from the log given below.
I'm using Veristand 2015 and LabView 2015 also. I set the inputs and outputs correctly in the connector pane, and when importing the model into Veristand, the inputs and outputs show up correctly. When I use the "Tools»NI VeriStand»Generate NI VeriStand Model from VI" There's no errors and it creates an LVmodel that I can import into veristand.
Is there any steps I could be missing? Or any troubleshooting advice for tweaking my design to accept an LVmodel?
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The VeriStand Gateway encountered an error while deploying the System Definition file.
Error -307703 occurred at Project Window.lvlib:Project Window.vi >> Project Window.lvlib:Command Loop.vi >> NI_VS Workspace ExecutionAPI.lvlib:NI VeriStand - Connect to System.vi
NI VeriStand: The specified model is incompatible with NI VeriStand. If you are trying to deploy the model to an RT target, launch the Console Viewer tool to display the console output of the target, which includes information about the source of the error.
NI VeriStand: NI VeriStand Engine.lvlib:VeriStand Engine Wrapper (RT).vi >> NI VeriStand Engine.lvlib:VeriStand Engine.vi >> NI VeriStand Engine.lvlib:VeriStand Engine State Machine.vi >> Model Execution.lvlib:Initialize Model Loop Data.vi >> SIT Model API.lvlib:Initialize Model.vi
NI VeriStand: Initialization error code 1
Solved! Go to Solution.
What is you LabVIEW model comprised of? What specific toolkits or packages?
Can you provide some screen shots?
Are you deploying to an RT target?
The actual model is very simple. I decided to try with a small model to start replacing some of the calculated channels in veristand. My VI takes frequency and duty cycle and calculates high and low times of a signal for FPGA generation of the signal. So it's really just a few simply arithmetic gates.
I am deploying to a RT target, is there special considerations for that?
CLA, CTA, CLED
It is using PharLap. We used a contractor to design and build the system, and they've used an LV model on the system already, it. I'm starting to dig into all this stuff, so I'm not sure of the system specifics. But by all accounts it should work for me too.
Here's something you might find helpful:
I also want to point out that your "High" unit is [volt-time], and your "Low" unit is [time - volt-time]. If those are the high and low times of your signal, the unit for both should be time.
To clarify a few things, I'm generating a model from LabView for Veristand, loading it into a Veristand project, and deploying it through that. So correct me if I'm wrong, but I don't think that link applies to my issue here. Also, I should have noted earlier, but the DC is the Duty Cycle of the signal, not voltage.
Thanks for clarifying.
First, let's take a step back and make sure that VeriStand can deploy at all. Can you successfully deploy to a Windows target?
Assuming that the Windows deployment is successful, have you tried following the step in the error message?
"If you are trying to deploy the model to an RT target, launch the Console Viewer tool to display the console output of the target, which includes information about the source of the error."
What exactly is your target?
A little more clarification. I have a Veristand project that deploys and runs just fine on our HiL system. But it's pure Veristand with the exception of a simulink model. But that deploys to the RT target and runs just fine. All I've done is replaced a small section of that project with a labview model. I've double and triple checked that the channels are hooked up correctly, and the error is always the same as my original posting. It doesn't like the model. So deploying in general isn't an issue. And the console viewer gives nothing new about the error. I can post the whole log if you want, but the only thing worth seeing is the error really.