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VeriStand error

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Hi,

 

When deploying a DLL-file from SimulationX on a cRIO 9002 I get the following error:

 

 

• Loading System Definition file: C:\Documents and Settings\All Users\Documents\National Instruments\NI VeriStand 2011\Projects\Untitled 1\Untitled 1.nivssdf
• Preparing to deploy the System Definition to the targets...
• Compiling the System Definition file...
• Initializing TCP subsystem...
• Starting TCP Loops...
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
The VeriStand Gateway encountered an error while deploying the System Definition file.

Details:
Error -307853 occurred at Project Window.lvlib:Project Window.vi >> Project Window.lvlib:Command Loop.vi >> NI_VS Workspace ExecutionAPI.lvlib:NI VeriStand - Connect to System.vi

Possible reason(s):

NI VeriStand: The VeriStand Gateway was unable to establish a connection with the target. Confirm that the target is running and that the VeriStand Engine successfully has started.
=========================
NI VeriStand: Server TCP Interface.lvlib:TCP Connection Manager.vi:1
<append>=========================
NI VeriStand: Error 63 occurred at TCP Open Connection in Server TCP Interface.lvlib:TCP Connection Manager.vi:1

Possible reason(s):

LabVIEW: Serial port receive buffer overflow.
=========================
LabVIEW: The network connection was refused by the server.
Target: 192.168.0.11

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
• Unloading System Definition file...

 

 

Any advice?

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Message 1 of 10
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I don't think the problem is with the dll... I exppect that you would receive a similar error even if you deployed an empty system definition.

 

The minimum system requirements for running NI VeriStand on an RT target is 128 MB of RAM.  Your 9002 is an older controller with only 32 MB of RAM, so I expect that you're running out of memory on your controller when you try to deploy.

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Message 2 of 10
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ok, so neither cRIO- 9002 nor -9004 have sufficient space to use Veristand? Are you familiar with the system requirements for LabVIEW Control & Design and whether there is enough RAM on the mentioned cRIOs if using that program instead of Veristand?

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Solution
Accepted by esplu88

I'm not sure what the requirements of the CD&Sim module are.  There is probably less overhead than running NIVS, so it might be possible, but I'm not sure.  Running your model DLL with the Simulation Interface Toolkit may be another option to consider.

 

If you do get your model running on your controller, keep in mind that the processor in the 9002 is also outdated, so your model may not run fast enough.  You may want to consider upgrading to a higher-performance RT controller if possible.

Message 4 of 10
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I get the same error as stated in the first post, except for I am trying to deploy a .nivssdf file to a PXI-8110 with an R series PXI-7813.  I have verified that the VeriStand RT Engine is installed on the target.  My .lvbitx file is up to date and coincides with my .fpgaconfig file.  The FPGA VI runs just fine in LabVIEW with simluated I/O and on the target FPGA.  I'm not sure what else might be relevant, but any idea what might cause this?

 

EDIT:  I just tried to deploy one of the examples (Engine Demo) and it does the same thing.  So it doesn't have anything to do with my specific project necessarily.

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Message 5 of 10
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Try reinstalling NIVS to the target through MAX.

 

(When you connect to a target that was running NIVS with LabVIEW, NIVS is disabled on the target until you reinstall)

Stephen B
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Message 6 of 10
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That seems to have fixed it.  Do you happen to know why this happens?  And is there a way around having to reinstall it every time I want to switch between running a target through LabVIEW and running it through VeriStand?

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Message 7 of 10
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Great!

 

It happens because NI VeriStand is actually a start up labview rtexe on the target. When the project connects, since you don't have the same startup application in the project... it clears it out on the target. I've filed a bug report (a long time ago unfortunatley) that this behavior shouldn't happen or at least be documented.

 

There is a fairly bad work around where you can backup the ni-rt.ini file before you connect from LV by FTP'ing into the target, and then replace it when you want to go back to NI VeriStand.

Stephen B
Message 8 of 10
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Well that sounds like a pain, haha.  I guess I'll just dedicate part of my work to "LabVIEW Development" and then to "VeriStand Development" or something.  It won't be a problem for the users, but as the developer I switch back and forth to test my FPGA code.  Perhaps I'll just use the simulated I/O function for development and then not have to worry about it.

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Message 9 of 10
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You could backup ni-rt.ini and than quickly restore it over FTP to get NI VeriStand back.

Jiri

CLA, CTA, CLED

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