# NI VeriStand

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## NI 9212 Thermocouple scaling in VeriStand

Hello,

I'm trying to get temperatures from a NI 9212 in VeriStand. For modules support reason (I also have a 9381 to use), I am not using the scan engine, but a custom FPGA personnality, returning the TCx and CJCx values.

My understanding of the 9212 is that CJC0 is related to TC0 to TC3, while CJC1 is related to TC4 to TC7 (it depends on the terminal block, thermistor included near the connectors).

VeriStand allow to set up scales, and I am wondering how to use it the best way. There is a scale type Thermocouple: I guess I have to use it, but how to define the CJC ?

So here is my hypothesis :

• Create a scale using following formula (see here), and apply it to the two CJC channels :
RT = [(CJC Data ÷ 0.078125) ÷ (1 – (CJC Data ÷ 0.078125))] × 28,000
This way, I am getting the actual resistor value according to the measured voltage, right ?
• Create a Thermocouple scale for each CJC, with Thermistor as CJC type, and point to the scaled thermistor value, CJC0 and CJC1
• Apply one of these scales to thermocouple channels (TC0:3 / TC4:7) to get a scaled temperature, according to the scaled thermistor value of CJC0 / CJC1

Is that correct ?

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## Re: NI 9212 Thermocouple scaling in VeriStand

Mathiu,

We have been using the 9213 T/C with a custom FPGA with VeriStand.  We use to have a custom device that would do the conversion, but with the addition of scales we just use that in VS.  I have attached some code snips.  We use a separate loop  for this T/C since it scans slower than most of our other cards, then just have it update through local vars to the main loop.  If you bring the CJC up to VS the scaling lets you map the CJC and does the conversion for you (At least for the 9213).

Good luck.

Josh

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## Re: NI 9212 Thermocouple scaling in VeriStand

Hi Josh,

Thanks for that quick answer (quicker than mine). I understand the idea, but I would prefer not having custom component - here a Custom Device in addition to the Custom FPGA (less custom, less support). That's why I wonder if my "two scales cascade" idea is mathematically correct. This requieres only a Custom FPGA (arleady done, due to 9381 support issue) and native VeriStand Scaling.

Regards,

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