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Issue while reading the outport in Veristand

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Issue while reading the outport in Veristand

Hello

We are placing an FPGA logic in FPGA custom personality, Logic here is to read the chassis temperature and display that value in Veristand, So we are using Veristand FPGA XML builder to get the input and output nodes. We are able to read the temperature output in Labview RT but when we deployed in Veristand RT we can't able to read the chassis temperature. Please find an attached image of the code.

Hardware used here is CRio-9074

Any reply would be greatly appreciated.

Thank You

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Re: Issue while reading the outport in Veristand

ani94,

 

This is a good start.  The XML Builder is a good way to integrate FPGA code into your VeriStand system.

 

First, make sure your datatypes match.  This interface into VeriStand is datatype aware - so if you mismatch them, it's at your own peril.  I would try to either more explicitly convert the values or configure the XML builder to float and fixed point, respectively.  (Though I forget if it has float...)

 

Second, can you post a screenshot of your system definition file?  You'll need to load both your bitfile and the XML (that gets generated from the XML builder) into the system definition.  The bitfile so VeriStand knows what to run, and the XML file so VeriStand knows how to talk to the DMA pipes that that node abstracts.

 

 

Andrew Heim
Systems Engineer
Endigit
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