Increase in HP Loop Duration on VeriStand2018 + PXIe-8840?

[Rokot]

We have a PXIe system consisting of:
Chassis PXIe-1082
Controller PXIe-8840 quad-core
2 * FPGA PXie-7822R
Software: VeriStand 2016
Matlab / Simulink 2013
The target is set to a clock rate of 5kHz and the model is made for it. PCL executes in low latency mode.
Now the effect is that after deploying the model, the HP Loop Duration is about 102μs. The Time Tep Duration of the model is 39-42μs large.
The CPU temperature is about 40 ° C and the CPU load about 39% of the first and fourth core.
After some time, the HP Loop Duration increases to 140μs, the Time Step Duration to 64μs. HP Count did not rise yet.
But we have already seen an HP loop duration of 180μs. The HP count also increased. Unfortunately, the CPU load and temperature were not recorded.
Question: What can lead to the big increases in HP Loop Duration? This is disproportionate to the increase in the time-step duration of the model. Does the model calculate any loops? Or is the controller down clocked because of the temperature?
How can we continue to investigate the effect? Maybe turn off some parts of the model and test?
Thanks for your suggestions.

[Rokot]

Now I've made the model with the NI configuration optimization "faster code" and it looks better. Immediately after deployment, the time step is 25us, HP Loop Duration at 100us. But after some hours it also increases, so that the time step becomes almost twice as big as at the beginning (45us). HP Loop Duraton is also rising (110-125us). But that does not lead to the HP Count.
However, the fundamental problem for us is that the time step actually increases over time. Something like a real-time system should not happen. I had this with another real-time system from another compancy only with a defective cooling.
Is it the behavior of PXI? I'll report that to NI because it does not meet our requirements for a real-time system.

[n_dakota]

Hello,

Just a quick thoughts:

1. What exactly are you trying to implement with your model? Could you elaborate a little bit more?

2. You seem to benchmark the temperature and CPU usage. Could you verify the memory usage as well?

3. Did you benchmark the model itself?

4. Try to run the model in parallel execution mode.

Hope it helps you get closer to solution.

[n_dakota]

One more question:

5. Is the loop time increasing continuously or there is some maximum that is reached and after the execution is stable?

[Rokot]

1. The model includes the hardware modeling of switching devices, logic of binary IOs, six power converters (two 4-quadrant choppers and four pulse-controlled inverters) and output of calculated model values (currents, voltages) to the FPGA, which are serial over 16 bits CON3 of the FPGA card. Each FPGA contains the modeling of a 4-quadrant chopper and two pulse-controlled inverters.
The two FPGAs receive the pulses from the ECUs and calculate the fast switching currents and voltages. The binary IOs are served with it.
The interface between the model and FPGAs is via DMA FIFO.

2. I will do it next step.
3. How can you benchmark the Simulink model?

4. We have to use the low latency mode, because for each clock the appropriate value must be calculated directly in the model and the calculated analog values must be output at this clock.

5. The maximum of the time step was with the fast coded model at 45-50 (starts at 25). Sometimes it sinks back to 40, rises again and so on.

Maimum of the hp loop duration at 115-130 (starts at 100).