03-14-2018 05:03 AM - edited 03-14-2018 05:05 AM
Hi,
maybe somebody could help me by answering this question: When using HWTSP mode, when exactly are new analog output samples generated with VeriStand?
Is it on the rising edge of the chassis master (PXI_TRIG0)? So far, my understanding was that VeriStand acquires new AI samples at the beginning of the PCL and generates new AO samples at the end of the PCL. If both AIs and AOs use the same trigger, that cannot be correct though.
Background:
We have several DAQ cards with HWTSP in the system definition. I'm now writing a custom device for one of those cards (PXIe 6363). I need to do this because I need a special logic that is not available when adding the DAQ devices to the system definition in the regular way. I want that the AO sample generation is synchronized with the AO sample generation of the other DAQ cards, which are configured by VeriStand. Can I just trigger on the rising edge of PXI_TRIG0 to do that?
Thanks,
Dirk
03-14-2018 10:38 AM - edited 03-14-2018 10:39 AM
Well, although not really VeriStand specific, I guess this link describes what is happening. I will go ahead and synchronize on PXI_TRIG0.
Regards
Dirk