FPGA Target Doesn't Run Faster Than 3Hz

[da123vid]

Hi,

I'm trying to use Veristand to run a Simulink control model on a NI 9074 (with 7 modules on it). The Simulink control should run at 100Hz. Some simple sensor signal computations need to run faster, that's why I'm using the FPGA mode. I've build my FPGA target in Labview, its running in Veristand, also with the Simulink model together, but only at maximum 3Hz instead of 100Hz.

When I set the target rate in the system explorer to a number below 3Hz it's adjusting the rate, but everything above 3Hz won't run faster. The same happens when I run the project without the Simulink model. Also a simple FPGA Target with only one in and one output won't run faster.

A simple Labview read-input-vi runs withe same cRio and on the same computer at 100Hz without any problems.

Did anyone experience something similar before and/or has suggestions?

Thanks,

David

[pipipi0405]

Did you compile your Simulink model as a DLL that works with VxWorks target (cRIO-9074)?

When you are running the project without the Simulink model, what is left running in the project?

Your Simulink DLL will run on the CPU, not on FPGA, so the model execution speed is dependent on your CPU spec on cRIO-9074. The trouble maybe that cRIO-9074 does not have enough CPU power to handle your Simulink model to run at 100Hz.

[da123vid]

The Simulink model is compiled for VxWorks and it's also running, but only with max 3Hz. 

When I run the project without the Simulink model I basically just read an output from my FPGA with a graph in my workspace. I can see that it's still to slow because the signal is to discrete and the time axis of the graph runs to slow (one second passes in (100Hz/3Hz) seconds).

So I don't think the problem is located in my Simulink model. Also, NI Max shows me that the cRio's CPU is at around 70% during this tests.

[wblfrank08]

Hi,

May I ask how do you tell the running rate from the workspace? can you be more specific? Besides, do you implement FPGA in veristand through the FPGA personality? Can you share the code? Maybe something wrong with the FPGA code?

Thanks!