05-09-2016 03:01 PM
Occasionally, I'm getting a couple errors regarding my FPGA which is configured in my VeriStand System Definition. These errors never occur after first booting up my real-time controller. It happens when I deploy a system definition for a subsequent run, it just doesn't happen every time.
The errors are -61207 and -63195 (in that order). The log can be found below.
Preparing to run system definition... Loading c:\ni-rt\NIVeriStand\SystemDefinitionData.nivscfg System Definition Details ----------------------------- Name: <Name of System Definition> Version: 1.0.0.377 Description: ----------------------------- Loading parameter file : c:\ni-rt\NIVeriStand\ParameterData.nivsparam Loaded 0 scales. Initializing DAQ devices... Initializing DAQ waveform tasks... Initializing engine timing sources... Initializing FPGA devices... **************************** System error encountered. :::Details::: Error code: -61207 Error Message: LabVIEW FPGA: Internal error: DiagramReset did not clear within the timeout period. Please contact National Instruments Technical Support at ni.com/support. **************************** System awaiting new configuration from client. Stopping system definition... Stop time: 12:09:33 05/09/2016 Finalizing engine timing sources... Finalizing inline custom devices... Finalizing DAQ devices... Finalizing FPGA devices... **************************** System error encountered. :::Details::: Error code: -63195 Error Message: NI-RIO: (Hex 0xFFFF0925) The handle for device communication is invalid or has been closed. Restart the application. **************************** System awaiting new configuration from client. Finalizing data sharing devices... Finalizing models... Unloading system definition... VeriStand Engine idle. Awaiting command... VeriStand Engine idle. Awaiting command...
We know that our application works because we have [ideally] identicaly hardware setups that also runs this system definition. So, I'm leaning toward some sort of driver and/or hardware issue. Rebooting just the real-time controller clears the issue but this is not an acceptable workaround.
Real-Time Controller: RMC-8354
FPGA: NI-9159
LabVIEW/VeriStand 2013 SP1
05-09-2016 04:03 PM
Current drivers:
NI-RIO 15.0
NI-DAQmx 14.2.0
NI-VISA 14.0.0
05-09-2016 09:11 PM
05-10-2016 09:17 AM
I saw that article but that doesn't apply to my situation. NI VeriStand is a deployed application and does not run interactively.
05-10-2016 09:23 AM
Do you have a custom device that is accessing the FPGA? I have had problems like this if I stop or abort the FPGA reference in the Custom Device rather than letting VS do it as part of its shutdown process.
05-10-2016 09:59 AM
We do not use any custom devices, just the default setup for FPGA.