I work with a cRIO-9035 and 3 times a cRIO-9141 chassis. The setup works well and I'm able to map all IOs in Veristand.
I realised that the Processor load of the cRIO-9035 lifts by ~50% after adding the Scan Engine & EtherCAT device in the Veristand System Definition.
I use LV and Veristand 2017.
Did I forget to pay attenetion to something which could reduce this processor load?
Thanks for your help
I have a cRIO 9074 and two analog cards NI 9205 and NI 9263 I realized after going to NI forums, I need to add a custom device "Scan Engine & Ethercat" in order to add C series modules in Veristand. I was able to add the scan engine & ethercat custom device on my veristand. When I tried to auto-detect modules, it would not detect either of the C series modules. I installed all the drivers which you mentioned in the previous post. I tried to manually add them but when I try to deploy it shows an error(Please find the attached image) and also I am not able to add the bitfile in user variables. It will be very helpful if someone can guide on this issue
1)I tried with Crio 9076 for scan engine and Ethercat custom device and I am able to detect the modules automatically when I press autodetect modules.
2) when I try to add the bit file in user variables I are not able to see the same interface(for ex: Image) and also it deselect the modules which were previously detected(In Image 1, slot 3 was available before selecting the bit file ), Is there any different procedure to compile the bit file for hybrid mode?
3) When I deploy this in Veristand RT it is showing an error(Please find the attached image 2)
If anyone assists me to solve this issue will be very helpful
Thanks & Regards
Anikethana M R
in order to use all the modules they all need to be added to the LabView real time project so they are part of the bitfile created. It is not possible to use individual modules in scan mode and others through the bitfile, they all have to be included in the bitfile.
I hope this helps,
I have added the required modules under both RT and FPGA. ie, since I'm trying to configure a hybrid mode and I need to access modules from both scan interface and FPGA mode, I have added NI 9205 under RT and NI 9263 under FPGA. We have created the bit file after adding these modules. However, we are still facing the same issue. Can you please let me know if there's any other procedure to follow while configuring a project in hybrid mode other than
looking at the error message from image 2 I think your problem is far simpler: one of the VIs you used is "broken". You can verify this by opening all the VIs and checking if they are executable. If not you have to correct the issue and rebuild it.
I also noticed that sometimes this is not spotted by the compiler at build time but only at runtime in Veristand, quite annoying..
I realized that but when I try to open the VI's it is showing LabVIEW load error code 3: Could not load front panel(VI library), I will attach the custom device file which I am using for my project can you please go through this and suggest me the steps to solve this issue. It will be a great help to me
Can anyone please share the Scan engine and Ethercat 2017 v4.4.1 version where all the VI can be open and executable.
I downloaded the
NI VeriStand 2017 with NI-RIO 17.0+ and EtherCAT 17.0+:
When I deployed in veristand RT it is showing an error(Please find the image 2) it says VI is not executable, So I tried to open the source code but it shows an error when I open the VI LabVIEW error code 3, Can anyone guide me to solve this issue