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Instruction Framework Tutorial

The attached .zip file contains a tutorial for getting started with the Instruction Framework library, a LabVIEW FPGA Instrument Design Library (IDL) used in several NI-provided sample project designs.  This tutorial will bring FPGA developers up to speed on basic Instruction Framework concepts, and how to get started with a simple design that uses the Instruction Framework.

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Required Software

This tutorial was created with the following software:

  1. LabVIEW 2014
  2. LabVIEW FPGA 2014
  3. FlexRIO 14.1

Newer versions which maintain backwards compatibility may work as well.


The Instruction Framework library evolved from the Register Bus library used in the VST LV FPGA designs.


The library defines two interfaces which may be implemented by clients.

  • Address Space
    • Receives instructions from the framework, and is expected to provide a response.
    • See instr.lib\_niInstr\Instruction Framework\v1\FPGA\Interfaces\Address Space\Address Space.lvclass
  • Instruction Producer
    • Sends instructions into the framework, and waits for a response.
    • See instr.lib\_niInstr\Instruction Framework\v1\FPGA\Interfaces\Instruction Producer\Instruction Producer.lvclass

At this time, the FIFO Register Bus is the only library with an Instruction Producer.

See instr.lib\_niInstr\FIFO Register Bus\v1\FPGA

This FIFO Register Bus library is nearly identical to the VST Register Bus, except this library implements the Instruction Producer interface that lets it hook into the Instruction Framework.  It may be worth noting that the FIFO Register Bus library also augmented the capabilities of the VST Register Bus by allowing for instructions with 64-bits of data, and a 32-bit address.

One of the benefits of using the Instruction Framework is that it provides encapsulation of details that you don't necessarily care about.  On VST, the Register Bus is placed in a SCTL at the top level of the design.  The instruction output from each Register Bus is passed to a network comprised of Register VIs, Arbiters, and Muxes, and the read data is passed back.  With Instruction Framework, you create a Register Configuration object, and connect Address Spaces and Instruction Producers using a simple registration API.

Some Instruction Framework features that were added:

  • Improved arbitration between shared subsystems (producers can talk to unblocked subsystems while shared subsystems are blocked)
  • Added inspection of attached address spaces / subsystems using metadata parameters: UID, instance number, parent.
  • Added version check capability using metadata parameters: version, oldest compatible version