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Host Memory Buffer for CompactRIO



This was released at NI Week 2017








CompactRIO targets currently support a few data transfer mechanisms for moving data between the RT processor and the FPGA. DMA channels are streaming pipes which are typically used for large quantities of data, like waveforms, or for sending control messages between targets. This mechanism is fast, but has high latency. Front panel controls and indicators are single-point register values which can be accessed individually by both RT and FPGA. Front panel controls have lower latency than DMA but access is element-by-element and requires a large amount of CPU interaction which can reduce performance of real-time control algorithms. Finally, the FPGA can signal interrupts on the RT controller, but this does not allow for transfer of data other than identifying which interrupt was set. In addition, these interrupts have relatively high jitter. Finally, Scan Engine uses DMA channels to transfer a large set of single-point data on a periodic basis. As it is based on the DMA transfer mechanism, the Scan Engine's update rate is fairly limited, usually 1-2 kHz on CompactRIO targets. All of these mechanisms require some interaction from the RT processor, and this can introduce jitter.   


Many control applications will use some combination of Scan Engine and/or front panel controls, as they depend on low latency, current value, single-point data updates. While these existing options are sufficient for most applications, certain extremely high performance applications are limited by the performance of these options rather than the available processing power.

Host memory buffer aims to provide a new option for these extremely high performance control applications for CompactRIO by providing a hardware-initiated bulk transfer mechanism which does not require interaction with the RT processor. This allows for the transfer of large data sets between targets with extremely low latency, close to that of a single front panel control interaction.

In this initial release, the FPGA is provided with direct access to the memory used by the RT processor. This offers high performance but there are no safeties in place to prevent access to the wrong memory location or to ensure coherent data transfer. In addition, this host memory buffer can only be accessed using the NI FPGA Interface C API.


The attached files include the files and executables necessary to correctly compile code utilizing the host memory buffer as well as a set of sample projects and a full install and development guide.   

Supported Hardware and Software:
LabVIEW, LabVIEW Real-Time, and LabVIEW FPGA 2014

C/C++ Development Tools for NI Linux Real-Time, Eclipse Edition 2014 

NI-RIO 14.0   
NI FPGA Interface C API 14.0

CompactRIO 906x targets
CompactRIO 903x targets
System on Module targets

Known Issues:
Caveats identified in installation document. This is required reading before use.

At present, this library is experimental, unsupported, and not recommended for production applications. Please see the licensing notice below. For the discussion around this API, please visit this community page.

NI Labs Licensing Notice:
Because the software technology available on NI Labs is experimental and has not yet been released for large-scale commercial use or fully tested by NI, the terms of the NI Labs license agreements vary from the standard NI software license terms. Further, the license terms for specific NI Labs technology may vary.  Please carefully read the terms of the license agreement included with each NI Labs download before accepting those terms. This library uses the NI Sample Code License which is included in the download package.